Deep Learning Compiler Optimization on Multi-Chiplet Architecture

Huiqing Xu, Kuang Mao, Quihong Pan, Zhaorong Tang, Mengdi Wang, Ying Wang
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Abstract

Multi-chiplet architecture can provide a high-performance solution for new tasks such as deep learning models. In order to fully utilize chiplets and accelerate the execution of deep learning models, we present a deep learning compilation optimization framework for chiplets, and propose a scheduling method based on data dependence. Experiments show that our method improves the compilation efficiency, and the performance of the scheduling scheme is at least 1-2 times higher than the traditional algorithms.
基于多芯片架构的深度学习编译器优化
多芯片架构可以为深度学习模型等新任务提供高性能的解决方案。为了充分利用小芯片,加快深度学习模型的执行速度,提出了一种小芯片深度学习编译优化框架,并提出了一种基于数据依赖的调度方法。实验表明,该方法提高了编译效率,调度方案的性能比传统算法至少提高1-2倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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