14th IEEE Symposium on High-Performance Interconnects (HOTI'06)最新文献

Designing Full-Connectivity WDM Optical Interconnects with Reduced Switching and Conversion Complexity 降低交换和转换复杂度的全连接WDM光互连设计

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.11

H. Hamza, J. Deogun

引用次数: 5

Fast Buffer Memory with Deterministic Packet Departures 具有确定性包偏离的快速缓冲存储器

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.13

Mayank Kabra, Siddharth Saha, Bill Lin

{"title":"Fast Buffer Memory with Deterministic Packet Departures","authors":"Mayank Kabra, Siddharth Saha, Bill Lin","doi":"10.1109/HOTI.2006.13","DOIUrl":"https://doi.org/10.1109/HOTI.2006.13","url":null,"abstract":"High-performance routers need to store temporarily a large number of packets in response to congestion. DRAM is typically used to implement the needed packet buffers, but DRAM devices are too slow to match the bandwidth requirements. To bridge the bandwidth gap, a number of hybrid SRAM/DRAM packet buffer architectures have been proposed (S. Iyer and N. Mckeown, 2002) (S. Kumar et al., 2005). These packet buffer architectures assume a very general model where the buffer consists of many logically separated FIFO queues that may be accessed in random order. For example, virtual output queues (VOQs) are used in crossbar routers, where each VOQ corresponds to a logical queue corresponding to a particular output. Depending on the scheduling algorithm used, the access pattern to these logical queues may indeed be at random. However, for a number of router architectures, this worst-case random access assumption is unnecessary since packet departure times are deterministic. One architecture is the switch-memory-switch router architecture (A. Prakash et al., 2002) (S. Iyer et al., 2002) that efficiently mimics an output queueing switch. Another architecture is the load-balanced router architecture (C.S. Chang et al., 2002) (I. Keslassy et al., 2003) that has interesting scalability properties. In these architectures, for best-effort routing, the departure times of packets can be deterministically calculated before inserting packets into packet buffers. In this paper, we describe a novel packet buffer architecture based on interleaved memories that takes advantage of the known packet departure times to achieve simplicity and determinism. The number of interleaved DRAM banks required to implement the proposed packet buffer architecture is independent of the number of logical queues, yet the proposed architecture can achieve the performance of an SRAM implementation","PeriodicalId":288349,"journal":{"name":"14th IEEE Symposium on High-Performance Interconnects (HOTI'06)","volume":"88 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114086291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform 基于ExpressEther - ethernet的可重构硬件平台虚拟化技术

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.12

Jun Suzuki, Y. Hidaka, J. Higuchi, T. Yoshikawa, A. Iwata

引用次数: 32

Loosely Coupled TCP Acceleration Architecture 松散耦合的TCP加速架构

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.18

Lea Shalev, Vadim Makhervaks, Zorik Machulsky, G. Biran, J. Satran, Muli Ben-Yehuda, Ilan Shimony

引用次数: 18

A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems 一种新的光互联高性能计算系统动态带宽重分配技术

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.6

Avinash Karanth Kodi, A. Louri

{"title":"A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems","authors":"Avinash Karanth Kodi, A. Louri","doi":"10.1109/HOTI.2006.6","DOIUrl":"https://doi.org/10.1109/HOTI.2006.6","url":null,"abstract":"As bit rates increase, optical interconnects based high-performance computing (HPC) systems improve performance by increasing the available bandwidth (using wavelength-division multiplexing (WDM) and space-division multiplexing (SDM)) and decreasing power dissipation as compared to traditional electrical interconnects. While static allocation of wavelengths (channels) in optical interconnects provide every node with equal opportunity for communication, it can lead to network congestion for non-uniform traffic patterns. In this paper, we propose an opto-electronic interconnect for designing a flexible, high-bandwidth, low-latency, dynamically reconfigurable architecture for scalable HPC systems. Reconfigurability is realized by monitoring traffic intensities, and implementing dynamic bandwidth re-allocation (DBR) technique that adapts to changes in communication patterns. We propose a DBR technique - lock-step (LS) that balances the load on each communication channel based on past utilization. Simulation results indicate that the reconfigured architecture shows 40% increased throughput and 20% reduced network latency as compared to HPC electrical networks","PeriodicalId":288349,"journal":{"name":"14th IEEE Symposium on High-Performance Interconnects (HOTI'06)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122214484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Case Study in I/O Disaggregation using PCI Express Advanced Switching Interconnect (ASI) 基于PCI Express高级交换互连(ASI)的I/O分解案例研究

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.5

V. Krishnan, Todd Comins, R. Stalzer, David Wong

{"title":"A Case Study in I/O Disaggregation using PCI Express Advanced Switching Interconnect (ASI)","authors":"V. Krishnan, Todd Comins, R. Stalzer, David Wong","doi":"10.1109/HOTI.2006.5","DOIUrl":"https://doi.org/10.1109/HOTI.2006.5","url":null,"abstract":"Decoupling the processor and I/O subsystem provides immense benefits that include high availability, efficient allocation and cost-effective upgrade of system resources. Such a disaggregation model calls for a high-performance interconnect to isolate the processor and I/O subsystem domains, yet provide the veneer of a single system. PCI express (PCIe) is one such interconnect and is becoming the de-facto I/O fabric. However, PCIe, as specified currently, provides limited support for I/O disaggregation and does not yet natively support dynamic sharing of I/O resources amongst processor subsystems - this is the next major step in I/O disaggregation. PCI express advanced switching interconnect (ASI) is well-suited for enhancing the capabilities of PCIe in a non-disruptive manner. ASI is built upon PCIe and has the innate ability to co-exist with PCIe devices due to its commonality of the link/physical layer with PCIe as well as its native support for encapsulating PCIe packets. Towards a simple yet illustrative demonstration of ASI-based disaggregation of PCIe devices, we employed StarGen's ASI products for creating a basic ASI fabric and disaggregated a PCIe based GigE NIC from a host system. The initial set of results showed a marginal effect on the application's latency, but contrary to expectations, the throughput was significantly impacted. Further analysis revealed that this unexpected drop in throughput could be rectified easily and indeed, the final results confirm that the use of ASI for supporting I/O disaggregation does not result in sub-optimal utilization of the GigE NIC","PeriodicalId":288349,"journal":{"name":"14th IEEE Symposium on High-Performance Interconnects (HOTI'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Scheduling Traffic Matrices On General Switch Fabrics 在一般交换结构上调度流量矩阵

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.22

Xiang Wu, A. Prakash, M. Mohiyuddin, A. Aziz

引用次数: 4

Strictly Nonblocking Multicasting WDM Optical Cross Connects Using Multiwavelength Converters 使用多波长转换器的严格无阻塞多播WDM光交叉连接

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.24

H. Hamza, J. Deogun

引用次数: 5

A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing 多千兆速度基于内容路由的可重构架构

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.7

J. Moscola, Young-Hee Cho, J. Lockwood

{"title":"A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing","authors":"J. Moscola, Young-Hee Cho, J. Lockwood","doi":"10.1109/HOTI.2006.7","DOIUrl":"https://doi.org/10.1109/HOTI.2006.7","url":null,"abstract":"This paper presents a reconfigurable architecture for high-speed content-based routing. Our architecture goes beyond simple pattern matching by implementing a parsing engine that defines the semantics of patterns that are parsed within the data stream. Defining the semantics of patterns allows for more accurate processing and routing of packets using any fields that appear within the payload of the packet. The architecture consists of several components, including a pattern matcher, a parsing structure, and a routing module. Both the pattern matcher and parsing structure are automatically generated using an application-specific compiler that is described in this paper. The compiler accepts a grammar specification as input and outputs a data parser in VHDL. The routing module receives control signals from both the pattern matcher and the parsing structure that aid in the routing of packets. We illustrate how a content-based router can be implemented with our technique using an XML parser as an example. The XML parser presented was designed, implemented, and tested in a Xilinx Virtex XCV2000E FPGA on the FPX platform. It is capable of processing 32-bits of data per clock cycle and runs at 100 MHz. This allows the system to process and route XML messages at 3.2 Gbps","PeriodicalId":288349,"journal":{"name":"14th IEEE Symposium on High-Performance Interconnects (HOTI'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A Single-Cycle Multi-Match Packet Classification Engine Using TCAMs 基于tcam的单周期多匹配包分类引擎

14th IEEE Symposium on High-Performance Interconnects (HOTI'06) Pub Date : 2006-08-23 DOI: 10.1109/HOTI.2006.8

M. Nourani, M. Faezipour

引用次数: 14