Lea Shalev, Vadim Makhervaks, Zorik Machulsky, G. Biran, J. Satran, Muli Ben-Yehuda, Ilan Shimony
{"title":"Loosely Coupled TCP Acceleration Architecture","authors":"Lea Shalev, Vadim Makhervaks, Zorik Machulsky, G. Biran, J. Satran, Muli Ben-Yehuda, Ilan Shimony","doi":"10.1109/HOTI.2006.18","DOIUrl":null,"url":null,"abstract":"We present a novel approach for scalable network acceleration. The architecture uses limited hardware support and preserves protocol processing flexibility, combining the benefits of TCP offload and onload. The architecture is based on decoupling the data movement functions, accelerated by a hardware engine, from complex protocol processing, controlled by an isolated software entity running on a central CPU. These operate in parallel and interact asynchronously. We describe a prototype implementation which achieves multi-gigabit throughput with extremely low CPU utilization","PeriodicalId":288349,"journal":{"name":"14th IEEE Symposium on High-Performance Interconnects (HOTI'06)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th IEEE Symposium on High-Performance Interconnects (HOTI'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTI.2006.18","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
We present a novel approach for scalable network acceleration. The architecture uses limited hardware support and preserves protocol processing flexibility, combining the benefits of TCP offload and onload. The architecture is based on decoupling the data movement functions, accelerated by a hardware engine, from complex protocol processing, controlled by an isolated software entity running on a central CPU. These operate in parallel and interact asynchronously. We describe a prototype implementation which achieves multi-gigabit throughput with extremely low CPU utilization