发布求助
文献互助 智能选刊 最新文献

2008 IEEE Custom Integrated Circuits Conference最新文献

筛选
英文 中文
SiP for GSM/EDGE in CMOS technology 用于GSM/EDGE的CMOS技术的SiP
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672174
G. Puma, Ernst Kristan, Paolo De Nicola, C. Vannier, Braam Greyling, S. Piccolella
{"title":"SiP for GSM/EDGE in CMOS technology","authors":"G. Puma, Ernst Kristan, Paolo De Nicola, C. Vannier, Braam Greyling, S. Piccolella","doi":"10.1109/CICC.2008.4672174","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672174","url":null,"abstract":"The development in the field of RF and baseband (BB) integration in nanoscale CMOS technology for cellular systems over the last recent years has shown significant progress. The successful integration of the RF transceiver with digital baseband processor enables mobile phone manufacturer to build ultra-low cost phones for GSM/GPRS in CMOS technology. This trend towards continuous system integration for mobile phones with an advanced feature set providing high data rate communication, multimedia and camera capabilities. The support of various features requires a system solution including the power-management unit (PMU) with highly efficient DC-DC converters to reduce the overall power consumption. However, this imposes a major challenge for the integration of the RF due to crosstalk and thermal heating effects caused by the PMU and BB part.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantation 基于CMOS lsi的视网膜下植入多芯片柔性假体装置
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672087
T. Tokuda, S. Sawamura, Y. Terasawa, Y. Tano, J. Ohta
{"title":"CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantation","authors":"T. Tokuda, S. Sawamura, Y. Terasawa, Y. Tano, J. Ohta","doi":"10.1109/CICC.2008.4672087","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672087","url":null,"abstract":"A CMOS-based multi-chip flexible retinal stimulator with light-sensing function was designed. The light sensing function is implemented for light-controlled retinal stimulation in subretinal configuration. The basic functionality and feasibility of the multi-chip flexible retinal stimulator was confirmed. A photo-activating operation with adjustable photosensitivity was successfully implemented on the retinal stimulator without any additional input line. We demonstrated and characterized the photosensing function.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"47 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117232958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS direct conversion transmitter with integrated in-band harmonic suppression for IEEE 802.22 cognitive radio applications 用于IEEE 802.22认知无线电应用的集成带内谐波抑制的CMOS直接转换发射机
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672158
Jongsik Kim, Seungsoo Kim, Jaewook Shin, Youngcho Kim, Junki Min, Kihong Kim, Hyunchol Shin
{"title":"A CMOS direct conversion transmitter with integrated in-band harmonic suppression for IEEE 802.22 cognitive radio applications","authors":"Jongsik Kim, Seungsoo Kim, Jaewook Shin, Youngcho Kim, Junki Min, Kihong Kim, Hyunchol Shin","doi":"10.1109/CICC.2008.4672158","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672158","url":null,"abstract":"A CMOS direct conversion transmitter for IEEE 802.22 cognitive radio applications is presented. In-band harmonic distortions are effectively suppressed across the full TV band by exploiting single-conversion dual-path architecture with integrated harmonic rejecting mixers and RF tunable filters. A fractional-N synthesizer with a single LC VCO and a wideband muti-modulus (2/3/4/6/8/12/16/24) divider block provide multiphase LO signals. Implemented in 0.18 mum CMOS, the transmitter delivers 0-dBm with in-band distortions less than -42 dBc across 54 - 862 MHz band without off-chip filters. Image and LO leakage components are also suppressed below -45 dBc and -36 dBc, respectively, through calibration circuitry. Measured P1dB and OIP3 are +9 dBm and +20 dBm, respectively.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers 采用动态偏置放大器的2.5MHz BW和78dB SNDR delta-sigma调制器
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672030
Yan Wang, Kyehyung Lee, G. Temes
{"title":"A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers","authors":"Yan Wang, Kyehyung Lee, G. Temes","doi":"10.1109/CICC.2008.4672030","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672030","url":null,"abstract":"A new dynamically-biased scheme is proposed to implement a 13-bit delta-sigma modulator with a 2.5 MHz signal bandwidth. It uses the low-distortion architecture, and hence the opamp linearity requirements are greatly relaxed. Its noise-coupled and time-interleaved structure further decreases the power consumption. The prototype chip was fabricated in a 0.18 um CMOS technology. Experimental results show that 78 dB SNDR is achieved when it is clocked at 60 MHz sampling rate. With 1.6 V power supply, the power dissipation is 19.2 mW.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123484602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation 采用混沌PAM调制的SATA应用的3ghz扩频时钟发生器
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672118
Fabio Pareschi, G. Setti, R. Rovatti
{"title":"A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation","authors":"Fabio Pareschi, G. Setti, R. Rovatti","doi":"10.1109/CICC.2008.4672118","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672118","url":null,"abstract":"This paper proposes a prototype of a spread spectrum clock generator which is the first known specifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed in 0.13 mum CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27times0.78 mm2 and the power consumption is as low as 14.7 mW.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115572104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Early prediction of product performance and yield via technology benchmark 通过技术基准对产品性能和成品率进行早期预测
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672059
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, D. Lim, Sangyeun Cho
{"title":"Early prediction of product performance and yield via technology benchmark","authors":"Choongyeun Cho, Daeik D. Kim, Jonghae Kim, D. Lim, Sangyeun Cho","doi":"10.1109/CICC.2008.4672059","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672059","url":null,"abstract":"This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65 nm SOI CMOS technology are predicted within a 5% RMS error relative to mean.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128332283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement 用于提高良率的容差自旋转矩传递(STT) MRAM阵列
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672056
Jing Li, Haixin Liu, S. Salahuddin, K. Roy
{"title":"Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement","authors":"Jing Li, Haixin Liu, S. Salahuddin, K. Roy","doi":"10.1109/CICC.2008.4672056","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672056","url":null,"abstract":"Spin-Torque Transfer Magnetic RAM (STT MRAM) has emerged as a promising candidate for future universal memory. It not only combines the desirable attributes of all current memory technologies (SRAM, DRAM and flash memories) but also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough understanding of the interrelationship between design parameters and parametric failures of STT MRAM cell in presence of process variations. Based on comprehensive physics-based model, solving the Non-Equilibrium Greenpsilas Function (NEGF) formalism in the ballistic regime, we develop an optimization methodology for robust cell design (in 1T1M configuration) to account for both stability and cell area. Further, we propose an efficient circuit design for variation tolerance. The proposed technique can effectively decouple the conflicting design requirements of read/write stability and area in conventional 1T1M cell, leading to considerably improved yield of memory array. Simulation results show that in our proposed cell, the robustness (cell stability) is improved by 36% with only 9% area overhead.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129793303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A 1V downconversion filter using duty-cycle controlled bandwidth tuning 使用占空比控制带宽调谐的1V下变频滤波器
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672185
P. Kurahashi, P. Hanumolu, U. Moon
{"title":"A 1V downconversion filter using duty-cycle controlled bandwidth tuning","authors":"P. Kurahashi, P. Hanumolu, U. Moon","doi":"10.1109/CICC.2008.4672185","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672185","url":null,"abstract":"This paper describes a downconversion filter which uses variable delay clocks to simultaneously perform downconversion mixing and filter bandwidth tuning. This method of bandwidth tuning is highly linear and applicable to low supply voltages. The test chip fabricated in a 0.18 mum CMOS process achieves 19.2 dBV IIP3 at 1 V and has a bandwidth that is tunable over a -50% range. The downconversion filter mixes and filters an 830 MHz input to a nominal 300 kHz bandwidth at DC.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing 6.5 Gb/s背板发射机，6抽头FIR均衡器和可变抽头间距
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672161
M. Bichan, A. C. Carusone
{"title":"A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing","authors":"M. Bichan, A. C. Carusone","doi":"10.1109/CICC.2008.4672161","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672161","url":null,"abstract":"This paper presents a 6.5 Gb/s transmitter for use in backplane links. This transmitter incorporates a finite impulse response filter with programmable tap spacing in the output driver to compensate for intersymbol interference. Using jitter-minimizing tap weights computed using a behavioral model of the transmitter, it is shown that at 6.5 Gb/s peak-to-peak data-dependent jitter is reduced by over 50% by using a tap spacing of 0.53 unit intervals (UI) instead of the usual 1 UI.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130530862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme 具有串扰抑制方案的5gb /s/引脚DDR存储接口收发器
2008 IEEE Custom Integrated Circuits Conference Pub Date : 2008-11-17 DOI: 10.1109/CICC.2008.4672166
Kwang-Il Oh, L. Kim, Kwang-il Park, Young-Hyun Jun, Kinam Kim
{"title":"A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme","authors":"Kwang-Il Oh, L. Kim, Kwang-il Park, Young-Hyun Jun, Kinam Kim","doi":"10.1109/CICC.2008.4672166","DOIUrl":"https://doi.org/10.1109/CICC.2008.4672166","url":null,"abstract":"A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5-Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The p-p jitter of output data is 52.82-ps.","PeriodicalId":286154,"journal":{"name":"2008 IEEE Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127643056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信