Choongyeun Cho, Daeik D. Kim, Jonghae Kim, D. Lim, Sangyeun Cho
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引用次数: 4
摘要
本文提出了一种实用的方法来估计集成电路产品的性能和参数产量,仅从一组精心选择的现有电气测量,旨在在制造的早期阶段进行技术监测。我们证明了在65nm SOI CMOS技术中毫米波锁相环和类似产品的逻辑性能的组件相对于平均值的RMS误差在5%以内。
Early prediction of product performance and yield via technology benchmark
This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65 nm SOI CMOS technology are predicted within a 5% RMS error relative to mean.