2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第2页

Automatic concolic test generation with virtual prototypes for post-silicon validation 用于硅后验证的虚拟原型的自动共结测试生成

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691136

Kai Cong, Fei Xie, Li Lei

引用次数: 21

Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time 基于行标准单元布局的自对齐双模式分解在多项式时间内最优最小化重叠冲突

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691094

Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong

引用次数: 11

Optimization of interconnects between accelerators and shared memories in dark silicon 暗硅中加速器与共享存储器互连的优化

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691182

J. Cong, Bingjun Xiao

{"title":"Optimization of interconnects between accelerators and shared memories in dark silicon","authors":"J. Cong, Bingjun Xiao","doi":"10.1109/ICCAD.2013.6691182","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691182","url":null,"abstract":"Application-specific accelerators provide orders-of-magnitude improvement in energy-efficiency over CPUs, and accelerator-rich computing platforms are showing promise in the dark silicon age. Memory sharing among accelerators leads to huge transistor savings, but needs novel designs of interconnects between accelerators and shared memories. Accelerators run 100x faster than CPUs and post a high demand on data. This leads to resource-consuming interconnects if we follow the same design rules as those for interconnects between CPUs and shared memories, and simply duplicate the interconnect hardware to meet the accelerator data demand. In this work we develop a novel design of interconnects between accelerators and shared memories and exploit three optimization opportunities that emerge in accelerator-rich computing platforms: 1) The multiple data ports of the same accelerators are powered on/off together, and the competition for shared resources among these ports can be eliminated to save interconnect transistor cost; 2) In dark silicon, the number of active accelerators in an accelerator-rich platform is usually limited, and the interconnects can be partially populated to just fit the data access demand limited by the power budget; 3) The heterogeneity of accelerators leads to execution patterns among accelerators and, based on the probability analysis to identify these patterns, interconnects can be optimized for the expected utilization. Experiments show that our interconnect design outperforms prior work that was optimized for CPU cores or signal routing.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133622996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

ICCAD-2013 CAD contest in mask optimization and benchmark suite ICCAD-2013 CAD竞赛中的掩模优化和基准套件

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691131

Shayak Banerjee, Zhuo Li, S. Nassif

{"title":"ICCAD-2013 CAD contest in mask optimization and benchmark suite","authors":"Shayak Banerjee, Zhuo Li, S. Nassif","doi":"10.1109/ICCAD.2013.6691131","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691131","url":null,"abstract":"Optical microlithography is the technique of printing a set of shapes on a wafer using light transmitted through a template called a mask. Repeatedly printing and stacking such shapes on top of each other to build electrical circuits allows us to manufacture chips in high volume. However this technique has now reached its fundamental physical limits of resolution. Current 193nm wavelength light is no longer sufficient to reliably transfer patterns which are now in the sub-100nm dimensional range. This has led to increased research in optimizing lithographic masks to pre-compensate for distortions introduced by the lithographic process. This is called mask optimization. In this contest, students are provided with a sample lithographic model which simulates the transfer of a mask pattern on to wafer. The mask is assumed to be a pixelated template, where every pixel can be turned on or off, to indicate where light passes through, or is blocked. Contestants are also provided with models to predict the robustness of their pattern i.e. how much variability is in the transferred pattern. Given these tools, the objective is to minimize the variability in the wafer image, as measured by process variability (PV) bands. This is subject to the constraints of runtime and satisfying pattern fidelity i.e. the transferred pattern should resemble the target pattern. Benchmarks are provided in the form of collections of geometric shapes, each of which provides a challenge in printing at sub-wavelength.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132167286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 68

Improving platform energy-chip area trade-off in near-threshold computing environment 改进近阈值计算环境下平台能量-芯片面积权衡

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691138

Hao Wang, Abhishek A. Sinkar, N. Kim

引用次数: 7

Stochastic error rate estimation for adaptive speed control with field delay testing 带现场延迟测试的自适应速度控制随机误差率估计

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691105

Shoichi Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, T. Onoye

引用次数: 14

Hardware security: Threat models and metrics 硬件安全:威胁模型和度量

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.5555/2561828.2561985

M. Rostami, F. Koushanfar, Jeyavijayan Rajendran, R. Karri

引用次数: 123

Computer-aided design of electrical energy systems 电力系统的计算机辅助设计

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691118

Younghyun Kim, Donghwa Shin, Massimo Petricca, Sangyoung Park, M. Poncino, N. Chang

引用次数: 12

Aging-aware logic synthesis 感知老化的逻辑综合

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691098

Mojtaba Ebrahimi, Fabian Oboril, S. Kiamehr, M. Tahoori

{"title":"Aging-aware logic synthesis","authors":"Mojtaba Ebrahimi, Fabian Oboril, S. Kiamehr, M. Tahoori","doi":"10.1109/ICCAD.2013.6691098","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691098","url":null,"abstract":"As CMOS technology scales down into the nanometer regime, designers have to add pessimistic timing margins to the circuit as guardbands to avoid timing violations due to various reliability effects, in particular accelerated transistor aging. Since aging is workload-dependent, the aging rates of different paths are non-uniform, and hence, design time delay-balanced circuits become significantly unbalanced after some operational time. In this paper, an aging-aware logic synthesis approach is proposed to increase circuit lifetime with respect to a specific guardband. Our main objective is to optimize the design timing with respect to post-aging delay in a way that all paths reach the assigned guardband at the same time. In this regard, in an iterative process, after computing the post-aging delays, the lifetime is improved by putting tighter timing constraints on paths with higher aging rate and looser constraints on paths which have less post-aging delay than the desired guarband. The experimental results shows that the proposed approach improves circuit lifetime in average by more than 3X with negligible impact on area. Our approach is implemented on top of a commercial synthesis toolchain, and hence scales very well.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128392131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 58

Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method 基于逻辑努力法的多电压区FinFET电路的联合定径和自适应独立门控制

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691155

X. Lin, Yanzhi Wang, Massoud Pedram

{"title":"Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method","authors":"X. Lin, Yanzhi Wang, Massoud Pedram","doi":"10.1109/ICCAD.2013.6691155","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691155","url":null,"abstract":"FinFET has been proposed as an alternative for bulk CMOS in current and future technology nodes due to more effective channel control, reduced random dopant fluctuation, high ON/OFF current ratio, lower energy consumption, etc. Key characteristics of FinFET operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper first introduces an analytical transregional FinFET model with high accuracy in both sub- and near-threshold regimes. Next, the paper extends the well-known and widely-adopted logical effort delay calculation and optimization method to FinFET circuits operating in multiple voltage (sub/near/super-threshold) regimes. More specifically, a joint optimization of gate sizing and adaptive independent gate control is presented and solved in order to minimize the delay of FinFET circuits operating in multiple voltage regimes. Experimental results on a 32nm Predictive Technology Model for FinFET demonstrate the effectiveness of the proposed logical effort-based delay optimization framework.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131688771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31