2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献

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A high-performance triple patterning layout decomposer with balanced density 一种高性能、密度均衡的三重模式布局分解器
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691114
Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, K. Lucas, D. Pan
{"title":"A high-performance triple patterning layout decomposer with balanced density","authors":"Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, K. Lucas, D. Pan","doi":"10.1109/ICCAD.2013.6691114","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691114","url":null,"abstract":"Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion 增量多扫描链排序的ECO触发器插入
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691192
A. Kahng, Ilgweon Kang, S. Nath
{"title":"Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion","authors":"A. Kahng, Ilgweon Kang, S. Nath","doi":"10.1109/ICCAD.2013.6691192","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691192","url":null,"abstract":"Testability of ECO logic is currently a significant bottleneck in the SOC implementation flow. Front-end designers sometimes require large functional ECOs close to scheduled tapeout dates or for later design revisions. To avoid loss of test coverage, ECO flip-flops must be added into existing scan chains with minimal increase to test time and minimal impact on existing routing and timing slack. We address a new Incremental Multiple-Scan Chain Ordering problem formulation to automate the tedious and time-consuming process of scan stitching for large functional ECOs. We present a heuristic with clustering, incremental clustering and ordering steps to minimize the maximum chain length (test time), routing congestion, and disturbance to existing scan chains. Test times for our incremental scan chain solutions are reduced by 5.3%, and incremental wirelength costs are reduced by 45.71%, compared to manually-solved industrial testcases.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132445937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization 使用预测全局优化验证耦合环振荡器在可变性存在下的启动失败
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691161
Taehwan Kim, D. Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim
{"title":"Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization","authors":"Taehwan Kim, D. Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim","doi":"10.1109/ICCAD.2013.6691161","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691161","url":null,"abstract":"This paper describes a simulation-based approach to establish whether a ring-oscillator always converges to the correct mode of operation regardless of its initial conditions and variability conditions. The verification is performed using a predictive global optimization algorithm that looks for a problematic initial state from a discretized state space. The algorithm explores the initial states that can maximize the settling time for the oscillator to reach its final steady state. If any of these initial states visited during the search is found exhibiting false oscillation behaviors for certain variability conditions, the initial state is reported as problematic. On the other hand, if the initial state with the globally maximum settling time is found without discovering such problematic states, the oscillator is reported free of start-up failures. It can be shown that despite the finite number of initial state candidates considered and finite number of Monte-Carlo samples to model variability, the proposed algorithm can verify the oscillator to a prescribed confidence level. Demonstrated on various even-stage differential ring oscillators, the algorithm was able to validate the circuit for 99% yield with 99.9% confidence level by evaluating 7~60 initial states each with 1,000 Monte-Carlo samples. To our knowledge, this is the first algorithm ever reported to address start-up failures with variability.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124017858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automated generation of efficient instruction decoders for Instruction Set Simulators 指令集模拟器中高效指令解码器的自动生成
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.5555/2561828.2561972
Nicolas Fournel, Luc Michel, F. Pétrot
{"title":"Automated generation of efficient instruction decoders for Instruction Set Simulators","authors":"Nicolas Fournel, Luc Michel, F. Pétrot","doi":"10.5555/2561828.2561972","DOIUrl":"https://doi.org/10.5555/2561828.2561972","url":null,"abstract":"Fast Instruction Set Simulators (ISS) are a critical part of MPSoC design flows. The complexity of developing these ISS combined with the ability to extend instruction sets tend to make automated generation of ISS a need. One important part of every ISS is its instruction decoder, but as the encoding of instruction sets becomes less orthogonal because of the incremental addition of instructions, the generation of a decoder is not anymore an obvious task. In this paper, we present two automated decoder generation strategies that are able to handle non-orthogonal instruction encodings. The first one builds a decision tree that does not consider the instruction's occurrences while the second considers these frequencies. In both cases, we use binary decision diagrams to represent the instructions encodings and the complex conditions due to the non-orthogonality of the encodings in order to generate the decoders. Our experiments on the MIPS and ARM (including VFP and Neon extensions) instruction sets show that both algorithms produce efficient decoders, and that it is beneficial to consider instruction frequencies.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Comprehensive technique for designing and synthesizing TSV Fault-tolerant 3D clock trees TSV容错三维时钟树设计与合成的综合技术
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691190
Heechun Park, Taewhan Kim
{"title":"Comprehensive technique for designing and synthesizing TSV Fault-tolerant 3D clock trees","authors":"Heechun Park, Taewhan Kim","doi":"10.1109/ICCAD.2013.6691190","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691190","url":null,"abstract":"Recently, to cope with clock TSV (Through-Silicon-Via) reliability problem efficiently, a new circuit structure called TSV Fault-tolerant Unit (TFU) and the allocation method of TFUs have been proposed. However, the existing design methods partially or never addressed following key issues: (1) the feasibility of TSV pairing for TFU allocation, (2) maximizing TSV pairing, (3) supporting the slew and delay control capability in TFU for the cases of pre-bond testing as well as post-bond stage, and (4) minimizing the impact of TFU insertion on the clock skew of the whole 3D clock tree. In this work, we propose a full solution to the problem of designing and synthesizing TSV fault-tolerant clock tree from a 3D clock tree, which effectively addresses above key issues.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132992666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing 使用普通稀释操作共享的dmfb多反应物生物测定样品制备
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691180
Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang, Juinn-Dar Huang
{"title":"Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing","authors":"Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang, Juinn-Dar Huang","doi":"10.1109/ICCAD.2013.6691180","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691180","url":null,"abstract":"Sample preparation is an essential processing step in most biochemical applications. Various reactants are mixed together to produce a solution with the target concentration. Since reactants generally take a notable part of the cost in a bioassay, their usage should be minimized whenever possible. In this paper, we propose an algorithm, CoDOS, to prepare the target solution with many reactants using common dilution operation sharing on digital microfluidic biochips (DMFBs). CoDOS first represents the given target concentration as a recipe matrix, and then identifies rectangles in the matrix, where each rectangle indicates an opportunity of dilution operation sharing for reactant minimization. Experimental results demonstrate that CoDOS can achieve up to 27% of reactant saving as compared with the bit-scanning method in single-target sample preparation. Moreover, even if CoDOS is not developed for multi-target sample preparation, it still outperforms the recent state-of-the-art algorithm, RSMA. Hence, it is convincing that CoDOS is a better alternative for many-reactant sample preparation.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130459132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Simulation of temporal stochastic phenomena in electronic and biological systems: A comparative review, examples and synergies 电子和生物系统中时间随机现象的模拟:比较回顾、例子和协同作用
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691206
A. Demir, B. Erman
{"title":"Simulation of temporal stochastic phenomena in electronic and biological systems: A comparative review, examples and synergies","authors":"A. Demir, B. Erman","doi":"10.1109/ICCAD.2013.6691206","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691206","url":null,"abstract":"We concentrate on the temporal stochastic behavior of electronic and biological systems due to mainly intrinsic noise and fluctuation phenomena as opposed to extrinsic crosstalk-like interference or statistical variations in system parameters. We provide an overview of modeling and analysis techniques for noise and fluctuation phenomena in biological systems with comparisons to electronic systems. We present several examples where a synergistic cross-fertilization between the two disciplines seems promising. In particular, we discuss the characterization of conformational fluctuations in proteins, the simulation of stochastic behavior in intracellular processes, and the modeling of noise in biological neurons, neuronal networks, nervous system and the brain.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116662863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The impact of shallow trench isolation effects on circuit performance 浅沟隔离效应对电路性能的影响
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691134
Sravan K. Marella, S. Sapatnekar
{"title":"The impact of shallow trench isolation effects on circuit performance","authors":"Sravan K. Marella, S. Sapatnekar","doi":"10.1109/ICCAD.2013.6691134","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691134","url":null,"abstract":"In nanometer technologies, shallow trench isolation (STI) induces thermal residual stress in active silicon due to post-manufacturing thermal mismatch. The amount of STI around an active region depends on the layout of the design, and the biaxial stress due to STI results in placement-dependent variations in the the transistor mobilities and threshold voltages of the active devices. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level, and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123061668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Improved SAT-based ATPG: More constraints, better compaction 改进的基于sat的ATPG:更多的约束,更好的压缩
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691102
Stephan Eggersglüß, R. Wille, R. Drechsler
{"title":"Improved SAT-based ATPG: More constraints, better compaction","authors":"Stephan Eggersglüß, R. Wille, R. Drechsler","doi":"10.1109/ICCAD.2013.6691102","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691102","url":null,"abstract":"Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) is a robust alternative to classical structural ATPG. Due to the powerful reasoning engines of modern SAT solvers, SAT-based algorithms typically provide a high test coverage because of the ability to reliably classify hard-to-detect faults. However, a drawback of SAT-based ATPG is the test compaction ability. In this paper, we propose an enhanced dynamic test compaction approach which leverages the high implicative power of modern SAT solvers. Fault detection constraints are encoded into the SAT instance and a formal optimization procedure is applied to increase the detection ability of the generated tests. Experiments show that the proposed approach is able to achieve high compaction - for certain benchmarks even smaller test sets than the currently best known results are obtained.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126490848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation 克服SystemC符号仿真中的调度备选爆炸问题
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691189
Chun-Nan Chou, Chen-Kai Chu, Chung-Yang Huang
{"title":"Conquering the scheduling alternative explosion problem of SystemC symbolic simulation","authors":"Chun-Nan Chou, Chen-Kai Chu, Chung-Yang Huang","doi":"10.1109/ICCAD.2013.6691189","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691189","url":null,"abstract":"Due to the non-determinism of the SystemC scheduler, SystemC symbolic simulation faces a scalability issue. The issue stems from enumerating all scheduling alternatives such that all design behaviors can be captured assuredly. To conquer the scheduling alternative explosion problem, we first adopt symbolic partial order reduction to reduce the equivalent scheduling alternatives for exploration. Moreover, for those scheduling alternatives that cannot be reduced by partial order reduction, we merge their execution paths (and also states) into fewer ones to prevent the number of paths from explosion. The experimental results show that we achieve a tremendous scalability improvement by combining these two techniques together.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115438442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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