2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第3页

Why the design productivity gap never happened 为什么设计效率差距从未发生过

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691175

H. Foster

引用次数: 17

A Vectorless framework for power grid electromigration checking 电网电迁移检测的无矢量框架

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691170

M. Fawaz, S. Chatterjee, F. Najm

引用次数: 6

In-placement clock-tree aware multi-bit flip-flop generation for power optimization 用于功率优化的内置时钟树感知多比特触发器生成

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691177

Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin

引用次数: 20

PROTON: An automatic place-and-route tool for optical Networks-on-Chip 质子:用于光网络芯片的自动放置和路由工具

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691109

Anja Boos, L. Ramini, Ulf Schlichtmann, D. Bertozzi

{"title":"PROTON: An automatic place-and-route tool for optical Networks-on-Chip","authors":"Anja Boos, L. Ramini, Ulf Schlichtmann, D. Bertozzi","doi":"10.1109/ICCAD.2013.6691109","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691109","url":null,"abstract":"Optical Networks-on-Chip (ONoCs) are considered a promising way of improving power and bandwidth limitations in next generation multi- and many-core integrated systems. Today, most related research acknowledges the key role of the physical layer in assessing ONoC topologies (e.g., insertion loss), but overlooks the placement and routing stage in the design process, hence applying physical design considerations to topology logic schemes. Such a mismatch is fundamentally due to the lack of mature CAD tools for placement and routing of optical NoCs. The objective of this work is to bridge this gap: We propose PROTON, a fast tool for automatic placement and routing of ONoC topologies, which can support designers in quantifying the degradation of design quality metrics when moving from topology logic schemes to their physical implementation. This gap is especially relevant for Wavelength-Routed ONoCs (WRONoCs), where logic schemes typically make unrealistic assumptions about the placement of initiators and targets. For this reason, we put PROTON to work with the most promising WRONoC topologies and explore their physical design space given the placement and routing constraints of a 3D stacked system. We also compare automatically generated layouts with handcrafted ones reported in the literature for the same topologies and target system, and prove an insertion loss improvement by up to 150x. With PROTON the exploration of the physical design space of ONoC topologies is possible as well as their scalability analysis considering the layout.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131601124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Thread-criticality aware dynamic cache reconfiguration in multi-core system 多核系统中线程临界感知的动态缓存重构

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691151

Po-Yang Hsu, TingTing Hwang

引用次数: 6

Bayesian Model Fusion: A statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits 贝叶斯模型融合:复杂模拟和混合信号电路有效的硅前验证和硅后调谐的统计框架

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691204

Xin Li, Fa Wang, Shupeng Sun, Chenjie Gu

引用次数: 26

Performance boosting under reliability and power constraints 在可靠性和功率限制下提高性能

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691140

Youngtaek Kim, L. John, Indrani Paul, Srilatha Manne, M. Schulte

{"title":"Performance boosting under reliability and power constraints","authors":"Youngtaek Kim, L. John, Indrani Paul, Srilatha Manne, M. Schulte","doi":"10.1109/ICCAD.2013.6691140","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691140","url":null,"abstract":"Voltage droops resulting from inductive noise are common in state-of-the-art processors. Many of the techniques used to reduce energy consumption - clock gating, power gating, process shrinks, and voltage reduction - lead to increased voltage droops or increased sensitivity to voltage variations. Designers use voltage guardbands to minimize errors due to voltage fluctuations and inductive noise; however, this leads to lower performance because the voltage and frequency points are set to deal with voltage droops from a worst-case benchmark or stressmark. Although most applications do not approach the voltage droop caused by the stressmark, there is no mechanism to guarantee correct operation outside the tested range. In this paper, we examine floating-point issue throttling (FP throttling), a hardware technique that reduces worst-case voltage droop. By lowering the issue rate in the FP scheduler, the processor can significantly reduce the maximum voltage droop in the system. We show the impact of FP throttling on voltage droop, and translate this reduction in voltage droop to an increase in operating frequency (and hence increased performance) because an additional guardband is no longer required to guard against droops resulting from heavy FP usage. We then examine the impact of FP throttling and guardband reduction on the SPEC CPU2006 benchmarks and show that some benchmarks benefit from the frequency improvements with FP throttling while others suffer due to reduced FP throughput. Finally, we present two techniques to determine dynamically when to trade FP throughput for reduced voltage margin and increased frequency, and show performance improvements of up to 15% for CINT2006 benchmarks and up to 8% for CFP2006 benchmarks. Our studies are done on hardware in which FP units generate the worst-case voltage droop. The technique can be modified for architectures in which other units cause the worst droop.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125169669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Low-power timing closure methodology for ultra-low voltage designs 超低电压设计的低功率定时闭合方法

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691191

Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou

{"title":"Low-power timing closure methodology for ultra-low voltage designs","authors":"Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou","doi":"10.1109/ICCAD.2013.6691191","DOIUrl":"https://doi.org/10.1109/ICCAD.2013.6691191","url":null,"abstract":"As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power-mode-aware clock tree often suffers from a huge overhead on power consumption. Moreover, at the ULV level, since the setup time and the hold time of each register dramatically increase, the number of timing violations also increases greatly. However, the existing minimum padding technique cannot fix hold time violations in multiple power modes. Based on those two observations, in this paper, we propose a low-power timing closure methodology, which incorporates the synthesis of clock tree and data path, for multipower-mode ULV designs. Our low-power timing closure methodology has two main approaches. First, we use multiple power modes to build a power-mode-aware clock tree for reducing clock skew with very small power consumption. Second, we propose the first multi-power-mode minimum padding technique to fix all the hold time violations in all the power modes simultaneously. Experimental results consistently show that the integration of both approaches yields the best results.","PeriodicalId":278154,"journal":{"name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132788880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Digital logic with molecular reactions 分子反应的数字逻辑

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691194

Hua Jiang, Marc D. Riedel, K. Parhi

引用次数: 36

Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor 考虑电池与应用处理器热耦合的移动设备动态热管理

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2013-11-18 DOI: 10.1109/ICCAD.2013.6691125

Q. Xie, Jaemin Kim, Yanzhi Wang, Donghwa Shin, N. Chang, Massoud Pedram

引用次数: 57