{"title":"Reliability mechanism of the unprogrammed amorphous silicon antifuse","authors":"R. Wong, K. Gordon","doi":"10.1109/RELPHY.1994.307810","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307810","url":null,"abstract":"The electrical properties of the unprogrammed metal electrode amorphous silicon antifuse has been characterized. A model is proposed for the reliability mechanism. During a voltage stress, the leakage current through the antifuse creates localized states which increase the leakage current from 1 nA to tens of nA. The effect eventually saturates and can be annealed out. The amorphous silicon antifuse does not have a catastrophic failure mechanism such as the Time Dependent Dielectric Breakdown found in dielectric antifuses. The increase in the amorphous silicon antifuse leakage current is predictable and reproducible. The increase does not effect the reliability of the Field Programmable Gate Array which uses this antifuse as a programmable interconnect. The FPGA product has been stressed for 200 million equivalent device hours with a 7.0 volt static burn in with no failures.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121888593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Lukaszek, W. Dixon, M. Vella, C. Messick, S. Reno, J. Shideler
{"title":"Characterization of wafer charging mechanisms and oxide survival prediction methodology","authors":"W. Lukaszek, W. Dixon, M. Vella, C. Messick, S. Reno, J. Shideler","doi":"10.1109/RELPHY.1994.307816","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307816","url":null,"abstract":"Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the J-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the J-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q/sub bd/ distributions are known.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126403427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Yasuda, N. Ikeda, K. Ham, M. T. Takagi, I. Yoshii
{"title":"Relation between stress-induced leakage current and dielectric breakdown in SiN-based antifuses","authors":"H. Yasuda, N. Ikeda, K. Ham, M. T. Takagi, I. Yoshii","doi":"10.1109/RELPHY.1994.307833","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307833","url":null,"abstract":"Degradation process of metal-to-metal antifuses which use thin silicon nitride as dielectric layer under high field stress is studied in detail. Prior to dielectric breakdown, leakage current at stress voltage increases with large and complex fluctuations for any sample. So-called stress-induced leakage current at low voltages in current-voltage characteristics is also observed and it increases as the stress continues. It is shown that the stress-induced leakage current and the pre-breakdown leakage current with fluctuations are identical phenomena, and that the stress-induced leakage current strongly relates to the dielectric breakdown. Therefore,it is important to understand the mechanism of the stress-induced leakage current in order to improve antifuse reliabilities. Discrete two-step fluctuations on the stress-induced leakage currents at low voltages are found and the stress-induced leakage current is not proportional to antifuse areas. Considering these findings, it is concluded that the stress-induced leakage current flows through local spots. The conduction mechanism of the stress-induced leakage currents is also studied. The main conduction process in SiN films appears to be Frenkel-Poole conduction. We also find that as the stress continues, the barrier height between an electrode and a SiN film becomes lower and the dielectric constant becomes larger. It is also found that the appearance of the stress-induced leakage current in the I-V characteristics depends on the thickness of the barrier metal. Dielectric breakdown electric field and TDDB lifetime also show the same dependence. Considering the experimental results, the stress-leakage current is related to the electrode material.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ambient moisture characterization of thin small outline packages (TSOPs)","authors":"M. Prud'homme","doi":"10.1109/RELPHY.1994.307853","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307853","url":null,"abstract":"Two types of TSOPs were characterized with ambient preconditioning stresses to determine their true moisture sensitivity to solder reflow induced damage. The results reveal that traditional accelerated preconditioning stresses do not properly predict this package's moisture sensitivity. Furthermore, the current model for predicting reflow damage may be ineffective for thinner packages since it only considers the amount of moisture absorbed and not the distribution of moisture.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122456745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Built-in reliability through sodium elimination","authors":"Jeff Chinn, Y. Ho, Mike Chang, Siliconix","doi":"10.1109/RELPHY.1994.307829","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307829","url":null,"abstract":"Minute amounts of sodium can cause semiconductor devices to fail. Wafer processors have steadily reduced sodium content to increasingly low levels in the gate oxide area. However, levels as high as 5E18 cm/sup -3/ are still commonly detected around metal layers in the industry. The industry has until now relied on the BPSG layer to prevent penetration into the active gate area. This approach is usually effective, but not bulletproof. Pinholes or thin spots in BPSG film still allow sodium ions to seep through. This protective or inter-dielectric layer. As part of a strong commitment to achieve built-in reliability, Siliconix launched a project to totally eliminate sodium from its products. As reported in this paper. We have successfully reduced the presence of sodium down to the SIMS detection level.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115749711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Change of the failure mode of layered aluminum conductors by modification of overlying dielectric","authors":"D. Pramanik, V. Chowdhury, V. Jain","doi":"10.1109/RELPHY.1994.307826","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307826","url":null,"abstract":"The failure mode of multilayered Al interconnects changes from shorts due to extrusions to failures due to resistance increase when the overlying dielectric is modified. A thick rigid dielectric favors failures due to extrusions whereas a more flexible dielectric favors resistance increase. The dielectric effectively changes the mechanical behavior of the interconnect without changing the overall kinetics of mass accumulation and depletion and suggests a model where the final mode of failure is determined by the response of the interconnect to mechanical stresses.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124243234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Building reliability into a high performance 4-level metallization system","authors":"M. Dreyer, J. Mobr, T. Zirkie","doi":"10.1109/RELPHY.1994.307865","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307865","url":null,"abstract":"Building reliability into MLM systems implies an a priori understanding of the mechanisms leading to failure for a given metallization technology. We present one approach to 'building-in reliability', by developing a database of electro- and stress-migration, and microstructural data for several Al-Cu(1.5%):Ti-W metallurgies. By performing experiments that exceed the targets for a given technology, the key process and design parameters impacting reliability for subsequent technologies were identified. In this paper we present experimental results obtained developing this database. We also show the development of a simple predictive model, for lines and vias, based on the key process and design parameters. Our results highlight one approach used to develop a building-in reliability capability for complex MLM interconnect systems.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123195873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. I. Cole, J. Soden, J. L. Rife, D. Barton, C. Henderson
{"title":"Novel failure analysis techniques using photon probing with a scanning optical microscope","authors":"E. I. Cole, J. Soden, J. L. Rife, D. Barton, C. Henderson","doi":"10.1109/RELPHY.1994.307808","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307808","url":null,"abstract":"Three new failure analysis techniques for integrated circuits (ICs) have been developed using localized photon probing with a scanning optical microscope (SOM). The first two are light-induced voltage alteration (LIVA) imaging techniques that (1) localize open-circuited and damaged junctions and (2) image transistor logic states. The third technique uses the SOM to control logic states optically from the IC backside. LIVA images are produced by monitoring the voltage fluctuations of a constant current power supply as a laser beam is scanned over the IC. High selectivity for localizing defects has been demonstrated using the LIVA approach. Logic state mapping results, similar to previous work using biased optical beam induced current (OBIC) and laser probing approaches, have also been produced using LIVA. Application of the two LIVA based techniques to backside failure analysis has been demonstrated using an infrared laser source. Optical logic state control is based upon earlier work examining transistor response to photon injection. The physics of each method and their applications for failure analysis are described.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123238617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"dv/dt induced latching failure in 1200 V/400 A halfbridge IGBT modules","authors":"Wu-chen Wu, M. Held, N. Umbricht, A. Birolini","doi":"10.1109/RELPHY.1994.307804","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307804","url":null,"abstract":"A reliability investigation of 1200 V/400 A halfbridge IGBT modules by switching test is reported in this paper. Latch up failure was observed in the un-tested part of IGBT modules, which resulted in catastrophic craterlike melting pits in emitter bonding pads and then the tested part of IGBT modules was destroyed by very high power dissipation. Fast turn on due to a small gate resistance caused a high dv/dt (about 4000 Vspl mu/s) which triggered the latching failure.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124886177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Sakagami, N. Arai, H. Tsunoda, H. Egawa, Y. Yamaguchi, E. Kamiya, M. Takebuchi, K. Yamada, K. Yoshikawa, S. Mori
{"title":"The impact of intermetal dielectric layer and high temperature bake test on the reliability of nonvolatile memory devices","authors":"E. Sakagami, N. Arai, H. Tsunoda, H. Egawa, Y. Yamaguchi, E. Kamiya, M. Takebuchi, K. Yamada, K. Yoshikawa, S. Mori","doi":"10.1109/RELPHY.1994.307812","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307812","url":null,"abstract":"This paper describes the effects of water-related species contained in intermetal dielectric layers on the reliability of nonvolatile memory devices. Charge loss of the cells and hot-carrier (HC) lifetime degradation of peripheral N-channel MOSFETs due to the high temperature bake test are accelerated by the water-related species in the intermetal dielectric layer. The relation between the charge loss and the HC-lifetime degradation and the mechanism involved are discussed. Appropriate dielectric structures to minimize such degradation have been proposed for nonvolatile memory devices with double-metal structure and scaled narrow first metal gaps.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"1982 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125446938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}