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Proceedings of 1994 IEEE International Reliability Physics Symposium最新文献

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Mechanism for the n-field device failure in double level metal CMOS device 双能级金属CMOS器件n场失效机理研究
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307819
S. Kim, J. Paik, C. G. Ko
{"title":"Mechanism for the n-field device failure in double level metal CMOS device","authors":"S. Kim, J. Paik, C. G. Ko","doi":"10.1109/RELPHY.1994.307819","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307819","url":null,"abstract":"A new mechanism for the n-field device failure in double level metal CMOS integrated circuits using SOG (spin-on glass) films for intermetal oxide planarization is suggested. From the analysis of I-V curve for field devices, junction leakage current and C-V curves of the field oxide capacitor, it is deduced that the degradation in the n-channel isolation characteristics between n/sup +/ and n/sup +/ areas is closely related to the formation of a minority carrier generation center in the p-type silicon substrate, which can provide minority carriers of short generation life time, i.e. donors, rather than by positive charge formation in the field oxide.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124161983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of plasma-induced charging damage on n-channel and p-channel MOSFET hot carrier reliability 等离子体诱导充电损伤对n沟道和p沟道MOSFET热载流子可靠性的影响
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307859
R. R. Mistry, B. Fishbein, B. Doyle
{"title":"Effect of plasma-induced charging damage on n-channel and p-channel MOSFET hot carrier reliability","authors":"R. R. Mistry, B. Fishbein, B. Doyle","doi":"10.1109/RELPHY.1994.307859","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307859","url":null,"abstract":"We have investigated the impact of plasma-induced charging damage on the hot carrier reliability of n- and p-MOSFET's, including the examination of different stress bias regimes and the statistical distributions of hot carrier failure times. We found that when electron trapping determines hot carrier failure-as in p-MOSFETs stressed under the peak gate current condition-the median time-to-fail was dramatically reduced while the dispersion in the failure data was increased as plasma damage increased. Interface trap dominated hot carrier degradation-as in n-MOSFET's stressed under the peak substrate current condition or p-MOSFET's stressed at V/sub gs/=V/sub ds/-was not affected by plasma damage. Then both electron trapping and interface trap generation impact hot carrier degradation-as in n-MOSFET's stressed at V/sub gs/=V/sub ds/-plasma damage had a measurable but smaller effect on the failure statistics. These results are explained in terms of the differing impact of thermal annealing on bulk and interface traps. Finally, we show that reduced damage processes can mitigate the impact of plasma damage on MOSFET hot carrier robustness.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129435306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Two electromigration failure modes in polycrystalline aluminum interconnects 多晶铝互连中的两种电迁移失效模式
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307834
E.M. Atakov, J. Clement, B. Miner
{"title":"Two electromigration failure modes in polycrystalline aluminum interconnects","authors":"E.M. Atakov, J. Clement, B. Miner","doi":"10.1109/RELPHY.1994.307834","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307834","url":null,"abstract":"Grain-boundary (GB) erosion-type voids and transgranular slit-like voids are found to be two competing electromigration (EM) failure modes in partly-bamboo interconnects. The effects of metal microstructure, passivation thickness, line width and length, and EM stress conditions on the two failure modes were studied. The kinetics for GB-type failures is strongly affected by the threshold effect in polycrystalline segments and is well described by the Multi-Lognormal (MLN) function with stress-dependent number of elements. The model predicts that the EM resistance of partly-bamboo lines at VLSI operating conditions is limited by the slit failure mode, rather than by GB-type failures.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131999875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Base and collector leakage currents and their relevance to the reliability of AlGaAs/GaAs heterojunction bipolar transistors 基极和集电极泄漏电流及其与AlGaAs/GaAs异质结双极晶体管可靠性的关系
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307801
J. Liou, K. Parab, C.I. Huang, B. Bayraktaroglu, D. Williamson
{"title":"Base and collector leakage currents and their relevance to the reliability of AlGaAs/GaAs heterojunction bipolar transistors","authors":"J. Liou, K. Parab, C.I. Huang, B. Bayraktaroglu, D. Williamson","doi":"10.1109/RELPHY.1994.307801","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307801","url":null,"abstract":"Base and collector leakage currents are extremely important to AlGaAs/GaAs heterojunction bipolar transistor (HBT) d.c. characteristics, and a simple model to describe such currents is presented. This study suggests that these currents are originated from the electron and hole leakage through the dielectric layer at the emitter-base and base-collector peripheries, as well as through the n/sup +/-subcollector/semi-insulating-substrate interface. The relevance of the leakage currents to the post-burn-in HBT behavior (e.g., current-gain degradation) is also investigated.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130249639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Designing latchup robustness in a 0.35 /spl mu/m technology 在0.35 /spl mu/m技术下设计锁紧鲁棒性
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307823
A. Amerasekera, S. T. Selvam, R. Chapman
{"title":"Designing latchup robustness in a 0.35 /spl mu/m technology","authors":"A. Amerasekera, S. T. Selvam, R. Chapman","doi":"10.1109/RELPHY.1994.307823","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307823","url":null,"abstract":"We have explored the technology design space for latchup robustness in a deep submicron process. We show using experimental data that latchup robustness can be designed into a deep submicron technology without the use of retrograde wells or trench isolation. The main parameters affecting the latchup holding voltage and the trigger current have been investigated. The application of simulations and empirical models for tailoring latchup holding voltages are also discussed.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129983739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Impact of structure enhanced defects multiplication on junction leakage 结构增强缺陷倍增对结漏的影响
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307809
B. Tsui, Y. Hsieh, C.H. Chang
{"title":"Impact of structure enhanced defects multiplication on junction leakage","authors":"B. Tsui, Y. Hsieh, C.H. Chang","doi":"10.1109/RELPHY.1994.307809","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307809","url":null,"abstract":"A junction leakage mechanism induced by structure enhanced defects multiplication at bird's beak of field oxide (FOX) is reported for the first time. For the junction structure with poly-Si on FOX, the mask-edge-defects (MED) resulted from high dose implantation will lead to the formation of dislocations during back-end processing. The position of dislocations may be as deep as 1-2 /spl mu/m from Si surface. The stress induced by interlayer dielectric film is believed to be the driving force for the multiplication of dislocations. Process modifications, including implantation dosage reduction, screen oxide removal after implantation, post-implantation annealing, and implantation without screen oxide, are shown to be able to suppress the leakage current slightly. Thus, prevention of MED formation is believed to be a fundamental solution of this problem.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134149777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A new mechanism of pipeline defect formation in CMOS devices CMOS器件中管道缺陷形成的新机制
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307807
H. Belgal, G. Yuen, J. Grohs, L. Rozler, H. Gee, S. Broydo, H. Wegener, W. Owen, J. Drori
{"title":"A new mechanism of pipeline defect formation in CMOS devices","authors":"H. Belgal, G. Yuen, J. Grohs, L. Rozler, H. Gee, S. Broydo, H. Wegener, W. Owen, J. Drori","doi":"10.1109/RELPHY.1994.307807","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307807","url":null,"abstract":"Pipeline defects, also known as \"diffusion pipes\", were widely reported in bipolar devices. They were recently reported to occur in complementary metal-oxide-semiconductor (CMOS) devices. We report a new mechanism of the formation of pipeline defects in CMOS devices. Moderate dose (2E13-2E14 cm/sup -2/) arsenic implants, under certain process conditions, can result in pipeline defects causing leakage between implanted regions. Enhanced diffusion of phosphorus along oxidation induced defects formed as a result of implant damage is proposed as a mechanism for the formation of pipeline defects. A low temperature furnace recrystallization step in inert ambient prior to subsequent high temperature processing was found to be critical to eliminating this defect mechanism.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"60 32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Comparison of ESD protection capability of SOI and bulk CMOS output buffers SOI和CMOS输出缓冲器ESD保护能力的比较
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307821
M. Chan, S. S. Yuen, Zhi-Jian Ma, K. Y. Hui, P. K. Ko, C. Hu
{"title":"Comparison of ESD protection capability of SOI and bulk CMOS output buffers","authors":"M. Chan, S. S. Yuen, Zhi-Jian Ma, K. Y. Hui, P. K. Ko, C. Hu","doi":"10.1109/RELPHY.1994.307821","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307821","url":null,"abstract":"ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability problem in handling negative ESD discharge current. Bulk NMOS output buffers fabricated on the substrate of the same SOI wafers, after etching away the buried oxide, have been used to compare the ESD protection capability between bulk and SOI technologies. The ESD voltage sustained by these \"bulk\" NMOS buffers is about twice the voltage sustained by conventional SOI NMOS buffers. This scheme is proposed as an alternative ESD protection for SOI circuits. The effectiveness of ESD resistant design strategies developed in bulk-substrate technologies when transferred to SOI circuits is also discussed in this paper.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114299831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
In-depth resolutions of integrated circuits via X-ray based line modified asymmetric crystal topography 基于x射线线修正的非对称晶体形貌的集成电路深度分辨率
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307803
W. T. Beard, K. A. Green, X.J. Zhang, R. W. Armstrong
{"title":"In-depth resolutions of integrated circuits via X-ray based line modified asymmetric crystal topography","authors":"W. T. Beard, K. A. Green, X.J. Zhang, R. W. Armstrong","doi":"10.1109/RELPHY.1994.307803","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307803","url":null,"abstract":"X-ray diffraction topography is the name given to several X-ray diffraction techniques which permit the topography of planes within a crystal to be examined. The topographic techniques based on Bragg diffraction from a periodic crystal are extremely sensitive to imperfections and strains in the crystal, since any alteration to the interplanar spacing of the crystal will effect a corresponding change in the Bragg diffraction condition. Line modified asymmetric crystal topography (LM-ACT) is one such topographic technique which shows particular promise in the field of microelectronics. The LM-ACT system is designed with low angular divergence in the X-ray probe beam which allows details of device geometries on the order of microns to be resolved. A major advantage of LM-ACT is that it is a nondestructive technique. This paper describes the LM-ACT system and shows how the system has been applied to the study of integrated circuits after specific processing steps as well as with the final product.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121650394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The effect of polyimide surface morphology and chemistry on package cracking induced by interfacial delamination 聚酰亚胺表面形貌和化学性质对界面分层引起的封装开裂的影响
Proceedings of 1994 IEEE International Reliability Physics Symposium Pub Date : 1994-04-11 DOI: 10.1109/RELPHY.1994.307850
M. Amagai, M. Ohsumi, E. Kawasaki, R. Baumann, H. Kitagawa
{"title":"The effect of polyimide surface morphology and chemistry on package cracking induced by interfacial delamination","authors":"M. Amagai, M. Ohsumi, E. Kawasaki, R. Baumann, H. Kitagawa","doi":"10.1109/RELPHY.1994.307850","DOIUrl":"https://doi.org/10.1109/RELPHY.1994.307850","url":null,"abstract":"The increasingly severe demands of concurrently increasing die size while reducing package size have made the mechanical stability of novel surface mount technologies a primary concern. The dominant issue is device failure due to package cracking caused by interfacial delamination between the polyimide-coated chip surface and the epoxy molding resin. To investigate the effect of polyimide surface morphology and chemistry on molding resin adhesion, devices were fabricated with different types of epoxy molding resins, polyimides, reactive ion etch (RIE) treatments, cure temperatures, cure atmospheres, and cleaning chemicals. The samples were characterized with scanning acoustic tomography (SAT), X-ray photo emission spectroscopy (XPS), atomic force microscopy (AFM), Fourier transform infrared spectroscopy (FTIR), and various package-level reliability tests. The results of the characterizations and an explanation of the primary factors affecting interfacial adhesion are presented in this paper.<<ETX>>","PeriodicalId":276224,"journal":{"name":"Proceedings of 1994 IEEE International Reliability Physics Symposium","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125126217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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