2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)最新文献

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Control Strategies for Power Management of PV/Battery System with Electric Vehicle 电动汽车光伏/电池系统电源管理控制策略
C. Swetha, N. Jayalakshmi, K. Bhargavi, P. B. Nempu
{"title":"Control Strategies for Power Management of PV/Battery System with Electric Vehicle","authors":"C. Swetha, N. Jayalakshmi, K. Bhargavi, P. B. Nempu","doi":"10.1109/DISCOVER47552.2019.9008082","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008082","url":null,"abstract":"This paper proposes a sliding mode control technique for an electric vehicle (EV). In this system a PV source and the battery bank supply the EV power. The PI and PID are the generally used control techniques, which is used for DC/DC converters for energy management under sudden load variations. Compared to nonlinear control techniques, linear control strategies are not efficient during power management of the entire system. In this paper, nonlinear control technique named average sliding mode control (SMC) is implemented for proper switching actions of DC/DC converter. The average SMC is cascaded with PI controller and used for EV to charge the maximum amount of power. The effectiveness of proposed controller is validated in MATLAB/Simulink platform using escape ford EV model. Finally, the obtained results are compared and validated with the conventional I-V controller.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132345090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Predicting difficulties in Mask Ventilation using Machine Learning techniques 使用机器学习技术预测口罩通气困难
D. K. Sreekantha, Roline Stapny Saldanha, Jotsna Gowda Krishnappa, S. Mehandale, Rodrigues Rhea Carmel Glen, M. Prajna
{"title":"Predicting difficulties in Mask Ventilation using Machine Learning techniques","authors":"D. K. Sreekantha, Roline Stapny Saldanha, Jotsna Gowda Krishnappa, S. Mehandale, Rodrigues Rhea Carmel Glen, M. Prajna","doi":"10.1109/DISCOVER47552.2019.9008092","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008092","url":null,"abstract":"The oxygen is to be supplied constantly through the mask to a patient in the Operation Theater (OT) when performing an operation. Any interruption in oxygen or air supply to the patient may lead to severe bodily damage or even death of the patient. The mask ventilation can be categorized into 3 levels namely easy, difficult and impossible mask ventilation. An expert anesthesiologist can accurately predict the difficulties in mask ventilation. Currently, expert anesthesiologists use their experience to manually analyze the patient features and predict the difficulties in mask ventilation. So authors have implemented a software solution by applying machine learning algorithms to predict the difficulties in mask ventilation. Authors have identified twelve physical parameters of the patient that are significant in predicting the difficulties in mask ventilation. The representative patient data collected from hospital and the knowledge of experienced anesthesiologist is used to synthesize the data set. The data set is mined using machine learning algorithms namely Logistic Regression, Random Forest, Support Vector Machine, Naive Bayes and k-Nearest Neighbors. Logistic Regression algorithm is proved to be better in predicting the difficulties in Mask Ventilation.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114369893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Meessage from General Chair 主席的话
{"title":"Meessage from General Chair","authors":"","doi":"10.1109/discover47552.2019.9007915","DOIUrl":"https://doi.org/10.1109/discover47552.2019.9007915","url":null,"abstract":"","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Early Detection and Diminution of DDoS attack instigated by compromised switches on the controller in Software Defined Networks 软件定义网络中控制器交换机受损引发的DDoS攻击的早期检测与减少
S. R, Ashutosh Pattanaik, Anshul Gupta, A. Kanavalli
{"title":"Early Detection and Diminution of DDoS attack instigated by compromised switches on the controller in Software Defined Networks","authors":"S. R, Ashutosh Pattanaik, Anshul Gupta, A. Kanavalli","doi":"10.1109/DISCOVER47552.2019.9007925","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9007925","url":null,"abstract":"Software Defined Networks (SDN) provides separation of data plane and control plane, which can be used for implementing various network solutions like traffic engineering, intrusion detection load balancing, etc. However, there are few issues relating to SDN that needs to be addressed, one of them being Distributed Denial of Service (DDoS) attack on the centralized controller. Many researchers have contributed various solutions for identifying and mitigating such attacks. However, the intruders often find new ways of performing such DDoS attacks and hence the detection of such attacks takes more time and resources. In this paper, the aim is to demonstrate how a DDoS attack can be initiated on an SDN controller by the compromised switches whose idle and hard timeout values are manipulated to send repeated flow table entry requests to the controller. Furthermore, a solution is also proposed to detect such an attack within the second repeated request and mitigate it immediately. This solution is highly efficient as the attack is detected instantly instead of calculating a threshold based on the number of flow entry requests to identify whether the traffic is attack traffic or a genuine one.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Flexible Processor Architecture Design 灵活的处理器架构设计
Dvivedi Rohan Vipulkumar, P. V. Bhanu, J. Soumya
{"title":"Flexible Processor Architecture Design","authors":"Dvivedi Rohan Vipulkumar, P. V. Bhanu, J. Soumya","doi":"10.1109/DISCOVER47552.2019.9008052","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008052","url":null,"abstract":"This paper provides an alternative approach to the modern processor architecture design using a Transport Triggered Architecture (TTA). The aim has been focused on flexible computer architecture design, that can allow execution of multiple Instruction Sets (Hardware) or Byte Codes (Virtual Machines) to emulate other Instruction Set Architectures (ISAs). The idea is to design a vertical microcoded processor, that can enable basic register to register data transfer from one address to another using TTA system. This results in execution of complex instructions in a multi-cycle fashion. The target then boils down to convert any currently known instructions to just a mere multiple register to register word transfers that would in-turn invoke other combinational or sequential hardware modules to execute the instruction.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125366434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New RNS-To-Binary Converters for Three-Moduli Set ${2^{n+1}-1, 2^{n}-1, 2^{n+k}}$ 新RNS-To-Binary转换器Three-Moduli设置$ {2 ^ {n + 1} 1 2 ^ {n} 1 2 ^ {n + k} } $
P. S. Phalguna, D. Kamat, P. A. Ananda Mohan
{"title":"New RNS-To-Binary Converters for Three-Moduli Set ${2^{n+1}-1, 2^{n}-1, 2^{n+k}}$","authors":"P. S. Phalguna, D. Kamat, P. A. Ananda Mohan","doi":"10.1109/DISCOVER47552.2019.9007938","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9007938","url":null,"abstract":"This paper presents three reverse converters one using Mixed Radix Conversion (MRC) and other two based on Chinese Remainder Theorem (CRT) for three-moduli set ${2^{n+1}-1, 2^{n}-1, 2^{n+k}}$ which is an extension of a previously investigated three-moduli set ${2^{n+1}-1, 2^{n}, 2^{n}-1}$. The proposed converters are compared with reverse converters for three-moduli sets reported in literature regarding hardware requirement and conversion time for obtaining desired dynamic range.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Significance of 2R Continuous Mode Optical Regenerators (CMORs) in Optical Network Impaired by Optical Linear Crosstalk 2R连续模光再生器在受光线性串扰损害的光网络中的意义
Deepa Kulal, Krithika M. Pai, Raksha Padiyar, Priyanka Desai Kakade
{"title":"Significance of 2R Continuous Mode Optical Regenerators (CMORs) in Optical Network Impaired by Optical Linear Crosstalk","authors":"Deepa Kulal, Krithika M. Pai, Raksha Padiyar, Priyanka Desai Kakade","doi":"10.1109/DISCOVER47552.2019.9008100","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008100","url":null,"abstract":"Wavelength Division Multiplexing (WDM) is one of the enabling technology for all-optical network, but can lead to severe system performance degradation due to the inherent optical crosstalk. In this paper, an analytical model is presented to estimate the bit error rate (BER) of a CMOR cascade system in the presence of interferometric crosstalk. This paper investigates the effectiveness of CMOR cascade in the reduction of the BER degradation, caused by the optical crosstalk in addition to the ASE noise accumulation.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114943457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Study of Imaging the Cardiac Activation Sequences in Electrocardiology 心电中心脏激活序列的成像研究
V. Bhat, A. H
{"title":"A Study of Imaging the Cardiac Activation Sequences in Electrocardiology","authors":"V. Bhat, A. H","doi":"10.1109/DISCOVER47552.2019.9008081","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008081","url":null,"abstract":"The electrical impulses propagating on the heart muscles create a potential difference between intra and extra cellular space, called as transmembrane potentials. These wavefronts passing throughout the myocardium generates potential on the body surface, which can be measured in terms of Electrocardiogram (ECG). The cardiovascular diseases like arrhythmia, cardiomyopathy, and infarctions result in rupturing of myocardial cells that show either less magnitude or zero action potentials. In order to diagnose the locations of the ruptured cells, ECG is one of the main tests that is popularly used. But, ECG limits its ability to image cardiac activities in the heart level. The clinicians may have to use other imaging modalities/invasive methods to diagnose the diseases. Non- invasive imaging is thus challenging approach that would help clinicians to localize the ruptured cardiac region. In this, the forward problem of the heart is modeled based on uniform double layer theory. The activation waves are non-invasively imaged on the cardiac surface. The inverse study is extended to reconstruct depolarization waves from abnormal sites at left and right ventricle muscles (anterior and posterior) using Tikhonov regularization technique.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129596862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Operating Frequency Enhancement of Magnetic levitation system using fractional order $PI^{lambda}D^{mu}$ Controller: Design and Tuning 分数阶$PI^{lambda}D^{mu}$控制器提高磁悬浮系统工作频率:设计与整定
Samrat Banerjee, R. Mukherjee, Malobi Mukheriee, Somosree Sengupta, S. Pandey
{"title":"Operating Frequency Enhancement of Magnetic levitation system using fractional order $PI^{lambda}D^{mu}$ Controller: Design and Tuning","authors":"Samrat Banerjee, R. Mukherjee, Malobi Mukheriee, Somosree Sengupta, S. Pandey","doi":"10.1109/DISCOVER47552.2019.9008060","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008060","url":null,"abstract":"Magnetic Levitation System (MLS) is a challenging system as it is an open loop unstable system, but it has varied applications in various fields. In this paper, a fractional order controller for operating frequency enhancement of such a system is proposed. First the mathematical model of MLS was derived for tuning of the FOPID controller. Using this a graphical tuning method using frequency domain specification has been proposed to tune the fractional parameters. In order to validate the superiority of the proposed controller scheme, the simulation was done for which the FOMCON toolbox in MATLAB was used. The comparative results showed a significant improvement in the operating frequency, maintaining a low steady-state error and peak overshoot with respect to a PID controller.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121179243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation 使用rt级时钟门控和操作数隔离的功能单元的功耗降低
Rashmi Samanth, C. Chaitanya, G. S. Nayak
{"title":"Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation","authors":"Rashmi Samanth, C. Chaitanya, G. S. Nayak","doi":"10.1109/DISCOVER47552.2019.9008025","DOIUrl":"https://doi.org/10.1109/DISCOVER47552.2019.9008025","url":null,"abstract":"In present embedded processors power consumption is a critical issue. One of the most common functional units in any processor is the Arithmetic Logic Unit (ALU) which performs different arithmetic and logical operations. As the operations become more and more complex it requires more power for the execution. In this implementation, low power ALU is designed by taking advantage of the concepts of operand isolation and clock gating low power techniques. Operand isolation prevents the data inputs from being propagated to unused logic blocks. Clock gating technique supports existing synchronous circuits with some additional logics to prune the clock tree, thus disabling the parts of the circuitry that are not in use. To estimate the effectiveness of the proposed techniques, a set of data path benchmark circuits using Cadence standard 180nm technology. It shows 63.63% to 49% of reduction in power with the smallest area overhead.","PeriodicalId":274260,"journal":{"name":"2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126433817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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