Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation

Abstract

In present embedded processors power consumption is a critical issue. One of the most common functional units in any processor is the Arithmetic Logic Unit (ALU) which performs different arithmetic and logical operations. As the operations become more and more complex it requires more power for the execution. In this implementation, low power ALU is designed by taking advantage of the concepts of operand isolation and clock gating low power techniques. Operand isolation prevents the data inputs from being propagated to unused logic blocks. Clock gating technique supports existing synchronous circuits with some additional logics to prune the clock tree, thus disabling the parts of the circuitry that are not in use. To estimate the effectiveness of the proposed techniques, a set of data path benchmark circuits using Cadence standard 180nm technology. It shows 63.63% to 49% of reduction in power with the smallest area overhead.