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2007 IEEE International Symposium on Circuits and Systems最新文献

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Low-Power Low-Noise Neural Amplifier in 0.18μm FD-SOI Technology 0.18μm FD-SOI技术的低功耗低噪声神经放大器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378008
Donghwi Kim, R. Kamoua, M. Stanaćević
{"title":"Low-Power Low-Noise Neural Amplifier in 0.18μm FD-SOI Technology","authors":"Donghwi Kim, R. Kamoua, M. Stanaćević","doi":"10.1109/ISCAS.2007.378008","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378008","url":null,"abstract":"For recording of neural signals from large population of neurons, stringent constraints are imposed on the design of neural amplifiers. We have designed neural amplifier in FD-SOI technology in order to achieve lower power consumption, smaller area, and better noise efficiency factor compared to the standard bulk processes. A symmetric pseudo resistor was realized with resistances on the order of 1015Ω, enabling a low cut-off frequency of 0.6mHz. The designed neural amplifier occupies an area of 0.004mm2, with simulated performance demonstrating an input-referred noise of 3.07μVrms and a power consumption of 6μW.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125553665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation 一种改进的帧级流水线结构用于高分辨率视频运动估计
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378485
Weifeng He, Zhigang Mao
{"title":"An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation","authors":"Weifeng He, Zhigang Mao","doi":"10.1109/ISCAS.2007.378485","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378485","url":null,"abstract":"Frame-level pipelined motion estimation structure achieves high throughput by exploiting the explicit parallelism among motion estimation blocks. In this paper, an improved frame-level pipelined architecture for FSBM motion estimation is proposed. The design efforts are focused on reducing the size of internal data buffers and the hardware overheads for high resolution video motion estimation. Compared with previous high performance architectures, the proposed architecture employs the smallest number of data buffers as well as removes the data broadcasting operations and keeps nearly 100% fully pipelined computation. As a result, this architecture offers a feasible solution for SHDTV video pictures.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126631865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
HRTF Interpolation Through Direct Angular Parameterization 通过直接角参数化HRTF插值
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378028
F. P. Freeland, L. Biscainho, P. Diniz
{"title":"HRTF Interpolation Through Direct Angular Parameterization","authors":"F. P. Freeland, L. Biscainho, P. Diniz","doi":"10.1109/ISCAS.2007.378028","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378028","url":null,"abstract":"Under anechoic conditions, a system that generates 3D binaural sound should simulate the head-related transfer functions (HRTFs) that represent sound changes from the source to the listener's ears. Such a system could directly use HRTFs measured over a sphere around the listener. However, since it is not feasible to perform measurements for every position, practical systems interpolate the necessary functions between measured HRTFs. This paper proposes a generalization of the continuous variable digital delay (CVDD) described in the literature, yielding a two spatial-variable dependent transfer function. It performs a polynomial interpolation whose coefficients are optimized on a region over the sphere, so that the angular coordinates of any point inside the region map directly into the corresponding HRTFs. Performance assessment is done through graphical means. The issue of continuity in moving sound generation is also approached, through the combination of adjacent-region structures","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126828410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC H.264/AVC中解码器友好自适应去块滤波器(DF-ADF)模式的决定
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378671
Yu Hu, Qing Li, Siwei Ma, C.-C. Jay Kuo
{"title":"Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC","authors":"Yu Hu, Qing Li, Siwei Ma, C.-C. Jay Kuo","doi":"10.1109/ISCAS.2007.378671","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378671","url":null,"abstract":"Video encoding to yield a decoder-friendly H.264 bit stream that consumes less decoding power yet with little coding efficiency degradation is investigated in this work. The energy saving of the decoder relies on the use of adaptive deblocking filters (ADF). We first propose a power consumption model for the deblocking filter. Then, the encoder performs the rate-distortion-decoder complexity optimization (RDC) to save the decoder power needed for deblocking filter operations, which is called the decoder-friendly adaptive deblocking filter (DF-ADF) mode decision. The RDC optimization framework presents a way to balance coding efficiency and the ADF decoding cost in the mode decision process. The effectiveness of the proposed DF-ADF algorithm is demonstrated by experiments with diverse video contents and bit rates.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115252311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Deterministic DEM DAC Performance Analysis 确定性DEM DAC性能分析
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377881
Hanjun Jiang, Degang Chen, R. Geiger
{"title":"Deterministic DEM DAC Performance Analysis","authors":"Hanjun Jiang, Degang Chen, R. Geiger","doi":"10.1109/ISCAS.2007.377881","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377881","url":null,"abstract":"A rigorous and complete analysis of the deterministic DEM (DDEM) DAC performance is presented. With this analysis, DDEM DAC's equivalent linearity as ADC static linearity test stimulus source can be precisely predicted. Simulation result is given to validate this theoretical analysis.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116147509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog Emulation of a Reconfigurable Tap Changing Transformer 可重构分接变换变压器的模拟仿真
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378185
A. S. Leger, J. C. Jiménez, Agung Fu, Sanal Djimbinov, Sa Em Soeurn, Sun Sit Lwin, C. Nwankpa
{"title":"Analog Emulation of a Reconfigurable Tap Changing Transformer","authors":"A. S. Leger, J. C. Jiménez, Agung Fu, Sanal Djimbinov, Sa Em Soeurn, Sun Sit Lwin, C. Nwankpa","doi":"10.1109/ISCAS.2007.378185","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378185","url":null,"abstract":"Accurate analog models of power system components are required in order to realize an analog computation engine for power systems. Analog computation is an area of continued interest and has certain advantages over traditional digital computation. Among the advantages are physically realizable solutions and significantly faster computation times. This paper focuses on the development of a tap changing transformer model designed for a previously proposed method of analog power flow computation. Prior research in this field has modeled generators, loads and transmission lines. The transformer model proposed here provides a more accurate depiction of the network and captures the switching behavior of tap changing transformers. The transformer is modeled in analog form and a controller for the tap changing was developed in digital form. The model is verified via software simulation.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"102 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116520055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Algorithmic ADC Offset Compensation by Non-White Data Chopping 非白数据斩波的ADC偏移补偿算法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378496
S. Vitali, Giampaolo Cimatti, R. Rovatti, G. Setti
{"title":"Algorithmic ADC Offset Compensation by Non-White Data Chopping","authors":"S. Vitali, Giampaolo Cimatti, R. Rovatti, G. Setti","doi":"10.1109/ISCAS.2007.378496","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378496","url":null,"abstract":"This paper aims at investigating the impact of non-white chopping on the offset compensation performance of time-interleaved analog-to-digital converters. The theoretical framework for selecting optimal chopping sequences is given allowing fast offset compensation and good spectral shaping. Both the signal-to-noise ratio and the spurious-free dynamic range are improved significantly.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116528611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit 一种小面积、低功耗CMOS带隙参考电路
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377874
Savvas Koudounas, J. Georgiou
{"title":"A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit","authors":"Savvas Koudounas, J. Georgiou","doi":"10.1109/ISCAS.2007.377874","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377874","url":null,"abstract":"This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis, a high-performance design, in a 0.18mum CMOS process, is presented.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122367166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Optimized multi-path routing using dual decomposition for wireless video streaming 无线视频流的双分解优化多路径路由
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378132
Yifeng He, I. Lee, L. Guan
{"title":"Optimized multi-path routing using dual decomposition for wireless video streaming","authors":"Yifeng He, I. Lee, L. Guan","doi":"10.1109/ISCAS.2007.378132","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378132","url":null,"abstract":"For video streaming over wireless ad hoc networks, source rate allocation and routing scheme are two important issues. In this paper, we propose a fully distributed algorithm to jointly optimize the source rate and routing scheme. We use dual decomposition to separate the optimization problem into multiple subproblems, which are then solved in parallel. The distributed nature of the proposed algorithm is extremely adequate for wireless ad hoc networks. Simulation results show that the proposed routing scheme outperforms some existing multi-path routing schemes.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122542194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma Modulators 带通δ - σ调制器中二元加权DAC非线性的连续补偿
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378383
G. Gagnon, L. MacEachern
{"title":"Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma Modulators","authors":"G. Gagnon, L. MacEachern","doi":"10.1109/ISCAS.2007.378383","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378383","url":null,"abstract":"We present a novel calibration technique to compensate for DAC element mismatches in bandpass multibit delta-sigma (DeltaSigma) modulators. The proposed technique is purely digital and requires only a minor modification to the modulator loop. It is compatible with binary weighted element DACs and the storage requirements for the calibrated coefficients increases only linearly with the number of quantizer bits. The calibration is performed without breaking the loop, which allows continuous tracking of environmental drifts. Simulation results show a peak signal to noise and distortion ratio (SNDR) of 68 dB after calibration for a DAC with plusmn1% mismatches, a sinusoid input signal near 1/4 of the sampling frequency and an oversampling ratio of only 10. Those results represent a 26 dB improvement over the non-calibrated case while being within 2 dB of an ideal-DAC case.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122645053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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