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2007 IEEE International Symposium on Circuits and Systems最新文献

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Multi-level Order Reduction with Nonlinear Port Constraints 非线性端口约束下的多级阶约简
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-06-25 DOI: 10.1109/ISCAS.2007.378584
M. Ma, R. Khazaka
{"title":"Multi-level Order Reduction with Nonlinear Port Constraints","authors":"M. Ma, R. Khazaka","doi":"10.1109/ISCAS.2007.378584","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378584","url":null,"abstract":"In recent years, congruence transformation based model order reduction methods have proven to be an effective tool in dealing with increasing computational complexities which arise from the simulation of interconnect networks. However, most existing model order reduction methods are only efficient in coping with systems with small number of ports. Moreover, model order reduction methods based on Krylov subspace result in a macromodel which is not optimal. In this paper, a two-level reduction method is proposed to address the above two limitations. In the first level reduction, prior information about the types the loads that can be connected to the ports and their ranges of values is exploited to obtain a reduced macromodel whose size is not very sensitive to the number of ports. Since the first level reduction uses congruence transformation based on Krylov subspace techniques, which contain redundant information. This leads to a second level reduction using singular value decomposition. The proposed method is shown to produce a macromodel which is significantly smaller than standard methods.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129108330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Class AB Pseudo-Differential CMOS Squarer Circuit AB类伪差分CMOS平方电路
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-06-25 DOI: 10.1109/ISCAS.2007.377902
J. Ramírez-Angulo, R. Chintham, A. López-Martín, R. Carvajal
{"title":"Class AB Pseudo-Differential CMOS Squarer Circuit","authors":"J. Ramírez-Angulo, R. Chintham, A. López-Martín, R. Carvajal","doi":"10.1109/ISCAS.2007.377902","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377902","url":null,"abstract":"A novel squarer circuit is proposed. The circuit operates in class AB yielding maximum output currents not limited by the quiescent currents. Class AB operation at the input stage is achieved using a compact pseudo-differential pair. Measurement results for a 0.5mum CMOS technology are included that demonstrate the approach followed.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132013272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters 实现FIR滤波器的贪心公共子表达式消除算法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378369
S. Vijay, A. P. Vinod, E. Lai
{"title":"A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters","authors":"S. Vijay, A. P. Vinod, E. Lai","doi":"10.1109/ISCAS.2007.378369","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378369","url":null,"abstract":"The complexity of finite impulse response (FIR) filters is dominated by the number of adders (subtractors) used to implement the coefficient multipliers. A greedy common subexpression elimination (CSE) algorithm with a look-ahead method based on the canonic signed digit (CSD) representation of filter coefficients for implementing low complexity FIR filters is proposed in this paper. Our look-ahead algorithm chooses the maximum number of frequently occurring common subexpressions and hence reduces the number of adders required to implement the filter. This adder reduction is achieved without any increase in critical path length. Design examples of FIR filters show that the proposed method offers an average adder reduction of about 20% over the best known CSE method.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Multi-Stage MCTF Coding Efficiency Analysis with Directed-Tree Model 基于有向树模型的多阶段MCTF编码效率分析
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378010
Fengling Li, N. Ling, Stephen A. Chiappari
{"title":"Multi-Stage MCTF Coding Efficiency Analysis with Directed-Tree Model","authors":"Fengling Li, N. Ling, Stephen A. Chiappari","doi":"10.1109/ISCAS.2007.378010","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378010","url":null,"abstract":"Motion-compensated temporal filtering (MCTF) was believed to improve coding efficiency due to its temporal noise filtering capability. However, recent experimental results in scalable video coding (SVC) development revealed that MCTF update steps at the decoder side do not always contribute significantly to the coding efficiency. In this paper, we present a novel directed-tree model to analyze the lifting-based multi-decomposition stage MCTF coding efficiency. It shows that with skipping the inverse update steps at the decoder side, MCTF performance converges against an upper bound, which depends on the actual prediction and the adaptive weighting algorithms. The results in our study provide a theoretical justification for not including MCTF update steps in the decoding process for scalable video coding","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multipath Polyphase Circuits and their Application to RF Transceivers 多径多相电路及其在射频收发器中的应用
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378388
E. Klumperink, R. Shrestha, E. Mensink, G. Wienk, Z. Ru, B. Nauta
{"title":"Multipath Polyphase Circuits and their Application to RF Transceivers","authors":"E. Klumperink, R. Shrestha, E. Mensink, G. Wienk, Z. Ru, B. Nauta","doi":"10.1109/ISCAS.2007.378388","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378388","url":null,"abstract":"Nonlinearity and time-variance in radio frequency (RF) circuits leads to unwanted harmonics and intermodulation products, e.g. in power amplifiers and mixers. This paper reviews a recently proposed multipath polyphase circuit technique which can cancel such harmonics and intermodulation products. This will be illustrated using a power upconverter IC as an example. The upconverter works from DC to 2.4 GHz, and the multipath polyphase technique cleans its spectrum up to the 17th harmonic, keeping unwanted spurious responses more than 40dB below the carrier. The technique can also be useful for other applications, and some possible applications will be discussed.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement 一种超低功耗时延测量的自适应互相关导数算法
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378799
F. N. M. Pirchio, P. Julián, P. Mandolesi, A. Chacón-Rodríguez
{"title":"An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement","authors":"F. N. M. Pirchio, P. Julián, P. Mandolesi, A. Chacón-Rodríguez","doi":"10.1109/ISCAS.2007.378799","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378799","url":null,"abstract":"In this paper, we report a low power integrated circuit that implements an adaptive version of the cross-correlation derivative algorithm for the estimation of inter-aural time difference. The architecture and logic structure as well as measured results reporting the performance of the IC -fabricated in a standard CMOS 0.5 mum process - are shown.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"335 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process 基于65nm CMOS工艺的低成本三通道10位250MHz DAC IP
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378530
W. Chou, Shu-Chieh Yang, F. Hsueh, Heng-Chang Huang, C. Hsiao
{"title":"A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process","authors":"W. Chou, Shu-Chieh Yang, F. Hsueh, Heng-Chang Huang, C. Hsiao","doi":"10.1109/ISCAS.2007.378530","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378530","url":null,"abstract":"An area-optimized 10-bit current steering, triple-channel video DAC IP designed in 65nm, 1.2V/2.5V CMOS process is described. Each channel of DAC can drive an output load of 37.5 ohms to provide a maximum output voltage 1.278V. The measured DNL and INL at 250MHz are less than 1 LSB and 2 LSB, respectively. This DAC IP is optimized with small area for low cost embedded SOC applications. It has area of 0.22mm2, which is the smallest IP in market.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124440450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS Front-End for a Lossy Image Compression Sensor 有损图像压缩传感器的CMOS前端
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378763
Zhiqiang Lin, M. Hoffman, W. Leon-Salas, N. Schemm, S. Balkır
{"title":"A CMOS Front-End for a Lossy Image Compression Sensor","authors":"Zhiqiang Lin, M. Hoffman, W. Leon-Salas, N. Schemm, S. Balkır","doi":"10.1109/ISCAS.2007.378763","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378763","url":null,"abstract":"A CMOS image sensor has been designed to perform the front-end image decomposition in a prediction-SPIHT image compression scheme. The prediction circuitry based on charge sharing is integrated inside the sensor array to perform 3-level image decomposition. A CMOS test chip has been prototyped and tested. The test results justify the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate but with much less data readout volume. Also, the sensor can be used to achieve comparable compression performance with much lower computational complexity compared to 2D discrete wavelet transform (DWT) based image compression.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116935407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensor 宽动态范围，高速机器视觉与2×256像素时间对比视觉传感器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378266
C. Posch, M. Hofstätter, M. Litzenberger, D. Matolin, Nikolaus Donath, P. Schön, H. Garn
{"title":"Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensor","authors":"C. Posch, M. Hofstätter, M. Litzenberger, D. Matolin, Nikolaus Donath, P. Schön, H. Garn","doi":"10.1109/ISCAS.2007.378266","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378266","url":null,"abstract":"This paper presents a 2times256 pixel dual-line temporal contrast vision sensor and the use of this sensor in exemplary high-speed machine vision applications over a wide range of target illumination. The sensor combines an asynchronous, data-driven pixel circuit with an on-chip precision time-stamp generator and a 3-stage pipelined synchronous bus-arbiter. With a temporal resolution of down to 100ns, corresponding to a line rate of 10MHz, the sensor is ideal for high-speed machine vision tasks that do not rely on conventional image data. The output data rate depends on the dynamic contents of the target scene and is typically orders of magnitude lower than equivalent data output produced by conventional clocked line sensors in this type of applications. 120dB dynamic range makes high-speed operation possible at low lighting levels or uncontrolled lighting conditions. The sensor features two parallel pixel lines with a line separation of 250mum and a pixel pitch of 15mum. A prototype was fabricated in a standard 0.35mum CMOS technology. Results on high-speed edge angle resolution and edge gradient extraction as well as wide dynamic range operation are presented.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"127 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV Applications 数字电视中MPEG-2转H.264/AVC编码模式分析
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378428
Yi-Nung Liu, Chi-Sun Tang, Shao-Yi Chien
{"title":"Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV Applications","authors":"Yi-Nung Liu, Chi-Sun Tang, Shao-Yi Chien","doi":"10.1109/ISCAS.2007.378428","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378428","url":null,"abstract":"MPEG-2 to H.264/AVC transcoding is an important module for video recoding in digital TV applications. For pixel domain transcoding, MPEG-2 bitstream is decoded and then re-encoded by H.264 encoder. Since the behavior of the decoded video is different from the original video, in this paper, the performance of each coding mode is analyzed to select the effective coding tools. It is shown from the analysis that transcoding with motion estimation with only one reference frame and 16times16 block size and deblocking filter can achieve almost the same video quality with only 19% of the computation. The analysis result could be an important reference for the implementation of MPEG-2 to H.264 transcoder.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121109805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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