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2007 IEEE International Symposium on Circuits and Systems最新文献

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An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver 一种用于低中频接收机的I/Q通道时间交错带通σ - δ调制器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378129
Minho Kwon, G. Han
{"title":"An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver","authors":"Minho Kwon, G. Han","doi":"10.1109/ISCAS.2007.378129","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378129","url":null,"abstract":"This paper proposes a multiplexing scheme to realize an I/Q channel time-interleaved (TI) band-pass sigma-delta modulator (BPSDM) that shares OTAs to minimize power consumption and silicon area for a low-IF wireless receiver. The test chip was fabricated for a 10.7-MHz IF system with a 0.35-mum CMOS process. The measured peak SNDR for a 200-kHz bandwidth is approximately 73 dB. The power consumption of the fabricated chip is 61 mW with a 3.3-V supply and the silicon area is 1.78 mm2.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths 具有大I/O数据宽度的dram的高速，最小面积和低功耗SEC代码
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377984
S. Cha, H. Yoon
{"title":"High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths","authors":"S. Cha, H. Yoon","doi":"10.1109/ISCAS.2007.377984","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377984","url":null,"abstract":"Many ECCs have been proposed to enhance the reliability of DRAMs, but most of them lack in the aspects of practical feasibility. We prioritize on how well and efficiently code could be actually implemented and propose high speed, minimal area, and low power SEC code for DRAMs with large I/O data widths. The proposed code minimizes the column weight, row weight and total weight of the H-matrix. Consequently, the area overhead and power consumption of the check bit generator are reduced by 17.7% at the most. The propagation delay is also decreased by reducing the level of XOR trees. Moreover, maximal power reduction is possible as the optimal H-matrix variants can be formulated to specifically tailor for various system applications with different spatial and temporal data correlations.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127211475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient Thermal Via Planning for Placement of 3D Integrated Circuits 三维集成电路布置的高效热通孔规划
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378242
Jing Li, H. Miyashita
{"title":"Efficient Thermal Via Planning for Placement of 3D Integrated Circuits","authors":"Jing Li, H. Miyashita","doi":"10.1109/ISCAS.2007.378242","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378242","url":null,"abstract":"The 3-dimensional (3D) ICs' increased module density exacerbates the thermal hot-spot problem: A larger module packed into a smaller footprint produces a higher maximum temperature. Because of the significant impact of thermal via on lowering the thermal resistance of the chip, an appropriate thermal via management can be hoped to alleviate the unfavorable thermal phenomena of 3D ICs. In this paper, based on a finite difference (FD) thermal mesh model, we firstly present an iterative thermal via planning (FD-TVP) algorithm for 3D standard cell layout, and then two methods are devised to realize the thermal via density's minimization during the chip's placement stage: (1) one is FD-TVP-fast method, in which a thermal-aware gravity placement algorithm is followed by the FD-TVP operation; (2) the other is FD-TVP-placement, which is hoped to obtain a final placement with a good thermal characteristic by introducing FD-TVP to the gravity placement process. Finally, the simulations on the IBM-PLACE benchmarks demonstrate our algorithms can achieve the maximum and average temperature objectives while minimizing the thermal via utilization. Moreover, the comparison between the results of FD-TVP-fast and FD-TVP-placement is also shown","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127325784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Transistor channel dendrites implementing HMM classifiers 晶体管通道树突实现HMM分类器
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378287
P. Hasler, Scott Koziol, E. Farquhar, A. Basu
{"title":"Transistor channel dendrites implementing HMM classifiers","authors":"P. Hasler, Scott Koziol, E. Farquhar, A. Basu","doi":"10.1109/ISCAS.2007.378287","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378287","url":null,"abstract":"Recently the authors presented transistor channel models of biological channels and the resulting implementation towards building spiking nodes, synapses, and dendrites. The authors also discussed how to build reconfigurable dendrites using programmable analog techniques. With all of this technology components available, the authors begin to address the question of the computation model possible using a dendrite element, as well as a network of dendrite elements. The authors discuss the connection between a dendrite element and a hidden Markov model (HMM) classifier branch, as well as a network of dendrites and somas to create an HMM classifier typical of what is used in speech recognition systems. The authors present simulation and experimental results for the branch elements; the authors also present initial results for a small dendrite based classifier structure to show the similarities to the HMM paradigm.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127437522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
SiGe 77GHz Automotive Radar Technology SiGe 77GHz汽车雷达技术
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378362
W. Huang, J. John, S. Braithwaite, J. Kirchgessner, I. Lim, D. Morgan, Y. Park, S. Shams, I. To, P. Welch, R. Reuter, Hao Li, A. Ghazinour, P. Wennekers, Yi Yin
{"title":"SiGe 77GHz Automotive Radar Technology","authors":"W. Huang, J. John, S. Braithwaite, J. Kirchgessner, I. Lim, D. Morgan, Y. Park, S. Shams, I. To, P. Welch, R. Reuter, Hao Li, A. Ghazinour, P. Wennekers, Yi Yin","doi":"10.1109/ISCAS.2007.378362","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378362","url":null,"abstract":"Recent advancements in SiGe device development enable the realization of 77GHz automotive long range radar systems using relatively low-cost silicon technology. This paper will discuss technology requirements for the radar design and present examples of receiver and transmitter circuit implementations.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127536662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding 使用电平编码的两相双轨编码的电流模式片上互连
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377892
E. Nigussie, J. Plosila, J. Isoaho
{"title":"Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding","authors":"E. Nigussie, J. Plosila, J. Isoaho","doi":"10.1109/ISCAS.2007.377892","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377892","url":null,"abstract":"We present delay variations insensitive long on-chip interconnect implementation based on current mode signaling and level-encoded two-phase dual-rail (LEDR) encoding. LEDR encoding is chosen over the normal two-phase dual-rail encoding because its completion detection and decoding circuitry is faster and much simpler since detection is level based rather than transition. The communication latency of this interconnect at global lengths of the wires reduces by half compared to conventional voltage mode LEDR interconnect. This is due to current mode signaling, making it possible to achieve high speed without pipelining and/or using repeaters. Performance simulation shows that at 5 mm wire length the throughput of this interconnect is 1 Gbps per one dual-rail wire pair. The effect of crosstalk on signal propagation delay is analyzed using four-bit parallel data transfer with the worst-case switching pattern and transmission line model which have both capacitive and inductive coupling. The interconnect circuitry is designed and simulated using Cadence Analog Spectre and Hspice with 130 nm CMOS technology.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124736272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Studying Nonlinear Dynamical Systems on a Reconfigurable Analog Platform 基于可重构模拟平台的非线性动力系统研究
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378559
K. Odame, C. Twigg, A. Basu, P. Hasler
{"title":"Studying Nonlinear Dynamical Systems on a Reconfigurable Analog Platform","authors":"K. Odame, C. Twigg, A. Basu, P. Hasler","doi":"10.1109/ISCAS.2007.378559","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378559","url":null,"abstract":"We have developed a field programmable analog array (FPAA) that can be configured to synthesis and analyze a vast variety of circuits. This FPAA is a valuable platform for studying nonlinear dynamics in circuits, as it offers close to the flexibility of computer simulation, but with actual experimental results. We present data from a current mirror, a peak detector, and a second-order section","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125080363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Architecture for Multiple Reference Frame Variable Block Size Motion Estimation 多参考帧变块大小运动估计的体系结构
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377854
S. Warrington, S. Sudharsanan, W. Chan
{"title":"Architecture for Multiple Reference Frame Variable Block Size Motion Estimation","authors":"S. Warrington, S. Sudharsanan, W. Chan","doi":"10.1109/ISCAS.2007.377854","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377854","url":null,"abstract":"This paper proposes a high throughput variable block size motion estimation (VBSME) architecture supporting multiple reference frames (MRF). To enable best rate-distortion performance for different video contents, the architecture allows selection between high spatial resolution motion search over a single reference frame, or MRF search at a lower spatial resolution. Through synthesis of an ASIC implementation, the architecture is shown to be suitable for high definition video resolutions and frame rates. The architecture also provides a higher overall macroblock throughput than other VBSME architectures in the literature.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A NMR Optimized Bitrate Transcoder for MPEG-2/4 LC-AAC 一个核磁共振优化比特率转码器MPEG-2/4 LC-AAC
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378661
Te-Hsueh Lai, Chung-Neng Wang, Tihao Chiang
{"title":"A NMR Optimized Bitrate Transcoder for MPEG-2/4 LC-AAC","authors":"Te-Hsueh Lai, Chung-Neng Wang, Tihao Chiang","doi":"10.1109/ISCAS.2007.378661","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378661","url":null,"abstract":"This paper presents a noise-to-masking-ratio (NMR) optimized MPEG-2/4 AAC low-complexity (LC) transcoder, called as fast rate-distortion optimized transcoder (FRDOT). The FRDOT searches for the optimal scale factors under the NMR criterion according to the magnitudes of quantized input coefficients and the target bitrate. The computation of NMR difference is replaced by the derivation of signal-to-noise-ratio (SNR) difference since the audible masking thresholds of the original and transcoded bitstreams are identical. The SNR value is further converted to a noise-to-signal-ratio (NSR) to represent distortion energy of audio signals. With the NSR values, a table lookup technique is used to speed up the search of the optimal scalefactor increment. To further reduce the execution time, a bandwidth limiter is used to remove the iterative rate-distortion optimization of a frame. In addition, a bitrate control module is proposed to make the averaged bitrate of output bitstream close to the target bitrate. The results show that the FRDOT has smaller NMR values than the cascaded transcoder (CT) by 0.5-3.0 dB at different bitrates with 6-7 times speedup on the average.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Voltage Temperature-Independent Current Reference with no External Components 无外部元件的低压温度无关电流基准
2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.377875
B. Kelleci, A. Karsilayan
{"title":"Low-Voltage Temperature-Independent Current Reference with no External Components","authors":"B. Kelleci, A. Karsilayan","doi":"10.1109/ISCAS.2007.377875","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.377875","url":null,"abstract":"A low-voltage CMOS temperature-independent current reference is presented. The proposed circuit requires no external component for biasing. Temperature independent voltage is converted to current, and proper operation is guaranteed by a fast startup circuit. The reference current is designed scalable to allow changing the power consumption of the overall system dynamically. The circuit is fabricated in TSMC 0.18mum process and measurement results show less than plusmn100 nA variation between 22deg C and 100deg C.","PeriodicalId":274010,"journal":{"name":"2007 IEEE International Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125444956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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