Efficient Thermal Via Planning for Placement of 3D Integrated Circuits

Abstract

The 3-dimensional (3D) ICs' increased module density exacerbates the thermal hot-spot problem: A larger module packed into a smaller footprint produces a higher maximum temperature. Because of the significant impact of thermal via on lowering the thermal resistance of the chip, an appropriate thermal via management can be hoped to alleviate the unfavorable thermal phenomena of 3D ICs. In this paper, based on a finite difference (FD) thermal mesh model, we firstly present an iterative thermal via planning (FD-TVP) algorithm for 3D standard cell layout, and then two methods are devised to realize the thermal via density's minimization during the chip's placement stage: (1) one is FD-TVP-fast method, in which a thermal-aware gravity placement algorithm is followed by the FD-TVP operation; (2) the other is FD-TVP-placement, which is hoped to obtain a final placement with a good thermal characteristic by introducing FD-TVP to the gravity placement process. Finally, the simulations on the IBM-PLACE benchmarks demonstrate our algorithms can achieve the maximum and average temperature objectives while minimizing the thermal via utilization. Moreover, the comparison between the results of FD-TVP-fast and FD-TVP-placement is also shown