A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit

2007 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI:10.1109/ISCAS.2007.377874

Savvas Koudounas, J. Georgiou

引用次数: 12

Abstract

This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis, a high-performance design, in a 0.18mum CMOS process, is presented.

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一种小面积、低功耗CMOS带隙参考电路

提出了一种适用于低功耗应用的低电压、小面积CMOS带隙基准电路。通过利用电阻t网络与布局高效的运放补偿相结合，实现了显着的面积减少。一个完整的分析，包括双环稳定性，揭示了面积，环路增益，稳定性和偏移灵敏度之间的几个权衡。在此基础上，提出了一种0.18 μ m CMOS工艺的高性能设计方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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