ACM Great Lakes Symposium on VLSI最新文献_第8页

Variability-aware design of double gate FinFET-based current mirrors 基于finfet的双栅电流反射镜的可变感知设计

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591583

D. Ghai, S. Mohanty, G. Thakral, Oghenekarho Okobiah

引用次数: 4

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip 芯片上准时延不敏感网络中链路永久故障引起的死锁在线检测

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591518

Wei Song, Guangda Zhang, J. Garside

引用次数: 7

Generation of reduced analog circuit models using transient simulation traces 利用瞬态仿真走线生成简化的模拟电路模型

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591530

P. Winkler, Henda Aridhi, M. Zaki, S. Tahar

引用次数: 1

A dual-rail LUT for reconfigurable logic using null convention logic 用于使用空约定逻辑的可重构逻辑的双轨道LUT

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591589

Jing Yu, P. Beckett

引用次数: 0

A design flow for physical synthesis of digital cells with ASTRAN 用ASTRAN进行数字细胞物理合成的设计流程

ACM Great Lakes Symposium on VLSI Pub Date : 2014-05-20 DOI: 10.1145/2591513.2591577

A. Ziesemer, R. Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans

引用次数: 2

An efficient approach for designing and minimizing reversible programmable logic arrays 一种设计和最小化可逆可编程逻辑阵列的有效方法

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206834

Sajib Kumar Mitra, Lafifa Jamal, M. Kaneko, H. M. H. Babu

引用次数: 10

InMnAs magnetoresistive spin-diode logic InMnAs磁阻自旋二极管逻辑

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206833

J. Friedman, N. Rangaraju, Y. Ismail, B. Wessels

{"title":"InMnAs magnetoresistive spin-diode logic","authors":"J. Friedman, N. Rangaraju, Y. Ismail, B. Wessels","doi":"10.1145/2206781.2206833","DOIUrl":"https://doi.org/10.1145/2206781.2206833","url":null,"abstract":"Electronic computing relies on systematically controlling the flow of electrons to perform logical functions. Various technologies and logic families are used in modern computing, each with its own tradeoffs. In particular, diode logic allows for the execution of logic with many fewer devices than complementary metal-oxide-semiconductor (CMOS) architectures, which implies the potential to be faster, cheaper, and dissipate less power. It has heretofore been impossible to fully utilize diode logic, however, as standard diodes lack the capability of performing signal inversion. Here we create a binary logic family based on high and low current states in which the InMnAs magnetoresistive semiconductor heterojunction diodes implement the first complete logic family based solely on diodes. The diodes are used as switches by manipulating the magnetoresistance with control currents that generate magnetic fields through the junction. With this device structure, we present basis logic elements and complex circuits consisting of as few as 10% of the devices required in their conventional CMOS counterparts. These circuits are evaluated based on InMnAs experimental data, and design techniques are discussed. As Si scaling reaches its inherent limits, this spin-diode logic family is an intriguing potential replacement for CMOS technology due to its material characteristics and compact circuits.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links 具有多通道毫米波无线链路的CMOS兼容多核noc架构

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206822

Sujay Deb, Kevin Chang, Miralem Cosic, A. Ganguly, P. Pande, D. Heo, B. Belzer

引用次数: 21

A fully integrated switched-capacitor DC-DC converter with dual output for low power application 完全集成的开关电容DC-DC转换器，具有双输出，适用于低功耗应用

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206803

HeungJun Jeon, Yong-Bin Kim

{"title":"A fully integrated switched-capacitor DC-DC converter with dual output for low power application","authors":"HeungJun Jeon, Yong-Bin Kim","doi":"10.1145/2206781.2206803","DOIUrl":"https://doi.org/10.1145/2206781.2206803","url":null,"abstract":"This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports two regulated power supply voltages of 2.2V and 3.2V from 5V input supply and delivers the maximum load currents up to 8mA at both of the outputs. The entire converter system uses two 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter by means of averaging the 5V input and the generated lower output voltage (2.2V), which is generated from 2-to-1_dw converter. Since 2-to-1_up converter is less sensitive to the bottom-plate parasitic capacitance loss, they are implemented with MOS capacitors, which show higher capacitance density (2.7fF/μm2, α=6.5%) than MIM capacitors (1fF/μm2, α=2.5%) while they have bigger bottom-plate parasitic capacitance ratio (α). The proposed implementation saves the area and quiescent currents for the control blocks since each block shares required analog and digital control blocks. The proposed converter is designed using high-voltage 0.35μm BCDMOS technology. Both output voltages are regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift registers and digitally controlled oscillators (DCOs). Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the output voltage ripples of the both outputs less than 1% (<40mV) of the output voltages when 400pF of output buffer capacitors are used for both outputs.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130647856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

NBTI mitigation in microprocessor designs 微处理器设计中的NBTI缓解

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI: 10.1145/2206781.2206791

S. Corbetta, W. Fornaciari

引用次数: 12