完全集成的开关电容DC-DC转换器,具有双输出,适用于低功耗应用

HeungJun Jeon, Yong-Bin Kim
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引用次数: 10

摘要

本文介绍了一种完全集成的片上开关电容(SC) DC-DC转换器,该转换器支持2.2V和3.2V两个稳压电源电压,从5V输入电源,并在两个输出端提供最大负载电流高达8mA。整个转换器系统使用两个2对1转换器模块。上输出电压(3.2V)由2-to-1_up变换器通过平均5V输入和2-to-1_dw变换器产生的下输出电压(2.2V)而产生。由于2-to- 1up变换器对底板寄生电容损耗的敏感性较低,采用MOS电容实现,其电容密度(2.7fF/μm2, α=6.5%)高于MIM电容(1fF/μm2, α=2.5%),同时具有较大的底板寄生电容比(α)。所提出的实现节省了控制块的面积和静态电流,因为每个块共享所需的模拟和数字控制块。该转换器采用高压0.35μm BCDMOS技术设计。两个输出电压通过脉冲频率调制(PFM)技术调节,采用18位移位寄存器和数字控制振荡器(dco)。在5.4 ~ 43.2mW的宽输出功率范围内,变换器的平均效率为70.0%,峰值效率为71.4%。10相交错技术使两个输出均使用400pF的输出缓冲电容时,两个输出的输出电压纹波小于输出电压的1% (<40mV)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A fully integrated switched-capacitor DC-DC converter with dual output for low power application
This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports two regulated power supply voltages of 2.2V and 3.2V from 5V input supply and delivers the maximum load currents up to 8mA at both of the outputs. The entire converter system uses two 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter by means of averaging the 5V input and the generated lower output voltage (2.2V), which is generated from 2-to-1_dw converter. Since 2-to-1_up converter is less sensitive to the bottom-plate parasitic capacitance loss, they are implemented with MOS capacitors, which show higher capacitance density (2.7fF/μm2, α=6.5%) than MIM capacitors (1fF/μm2, α=2.5%) while they have bigger bottom-plate parasitic capacitance ratio (α). The proposed implementation saves the area and quiescent currents for the control blocks since each block shares required analog and digital control blocks. The proposed converter is designed using high-voltage 0.35μm BCDMOS technology. Both output voltages are regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift registers and digitally controlled oscillators (DCOs). Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the output voltage ripples of the both outputs less than 1% (<40mV) of the output voltages when 400pF of output buffer capacitors are used for both outputs.
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