A design flow for physical synthesis of digital cells with ASTRAN

A. Ziesemer, R. Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
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引用次数: 2

Abstract

As the foundries update their advanced processes with new complex design rules and cell libraries grow in size and complexity, the cost of library development become increasingly higher. In this work we present the methodology used in ASTRAN to allow automatic layout generation of cell libraries for technologies down to 45nm from its transistor level netlist description in SPICE format. It supports non-complementary logic cells, allowing generation of any kind of transistor networks, and continuous transistor sizing. We describe our new generation flow which is currently being used to generate a library with more than 500 asynchronous cells in a 65nm process.
用ASTRAN进行数字细胞物理合成的设计流程
随着晶圆代工厂采用新的复杂设计规则更新其先进工艺,单元库的规模和复杂性不断增加,单元库开发的成本越来越高。在这项工作中,我们介绍了ASTRAN中使用的方法,该方法允许从其晶体管级网络表描述中以SPICE格式自动生成低至45nm的技术的单元库。它支持非互补逻辑单元,允许生成任何类型的晶体管网络,以及连续的晶体管尺寸。我们描述了我们的新一代流程,该流程目前用于在65nm工艺中生成具有500多个异步单元的库。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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