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2020 International Conference on Electronics, Information, and Communication (ICEIC)最新文献

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An approximate DRAM with efficient refresh schemes for low power deep learning applications 一种近似的DRAM，具有高效的刷新方案，适用于低功耗深度学习应用
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051355
Duy-Thanh Nguyen, Hyuk-Jae Lee, Hyun Kim, I. Chang
{"title":"An approximate DRAM with efficient refresh schemes for low power deep learning applications","authors":"Duy-Thanh Nguyen, Hyuk-Jae Lee, Hyun Kim, I. Chang","doi":"10.1109/ICEIC49074.2020.9051355","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051355","url":null,"abstract":"To avoid the accuracy drop caused by slowing down the refresh rate of a DRAM, the proposed approximate DRAM flexibly controls the refresh operation for different bits of data. Data are reorganized and mapped to different DRAM devices according to their bit significance. More critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. Compared to the conventional DRAM, the proposed approximate DRAM requires only a separation of the chip select signal for each device in a DRAM rank and a minor change in the memory controller. Simulation results show that the refresh power consumption is reduced by 66.5 % with a negligible accuracy drop in computation for state-of-the-art deep networks.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124079316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Area-Efficient Fault Tolerant Design for Finite State Machines 有限状态机的区域有效容错设计
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051122
Soyeon Choi, Jiwoon Park, Hoyoung Yoo
{"title":"Area-Efficient Fault Tolerant Design for Finite State Machines","authors":"Soyeon Choi, Jiwoon Park, Hoyoung Yoo","doi":"10.1109/ICEIC49074.2020.9051122","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051122","url":null,"abstract":"The finite state machine (FSM) controls the operation of the entire system. Therefore, if the errors occur in the FSM, it causes serious problem of the system. The fault tolerant state machine is proposed to deal with the errors in the FSM. In this paper, we propose a selective fault-tolerant finite state machine that increases fault-tolerance by applying the fault-tolerant circuit selectively according to the importance of state. The proposed SFT-FSM is 39% smaller when the redundancy factor $pmb{N}$ is 9, compared to the FSM with NMR technique.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121468242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Efficient Proposed Yangon Railway System Simulation Module 一个高效的仰光铁路系统仿真模块
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051336
Htain Lynn Aung, P. Sasithong, Irfan Ullah, M. Pengnoo, L. Wuttisittikulkij, W. Pirom, Suvit Poomrittigul, S. Wijayasekara
{"title":"An Efficient Proposed Yangon Railway System Simulation Module","authors":"Htain Lynn Aung, P. Sasithong, Irfan Ullah, M. Pengnoo, L. Wuttisittikulkij, W. Pirom, Suvit Poomrittigul, S. Wijayasekara","doi":"10.1109/ICEIC49074.2020.9051336","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051336","url":null,"abstract":"Public transportation is significant in an economical city like Yangon. In Yangon, there are four types of public transport facilities; mostly peoples can choose bus, train, taxi and water bus particularly. Railway system in Yangon city is not very developed. Most of the peoples have to depend on the buses system in the city. The massive amount of using buses in the city as the disadvantages; it can lead to traffic jam and air pollution. In this research article, we proposed an efficient software tool with user-friendly Graphical User Interface (GUI) that can help to upgrade the Yangon city railway system to the intelligent railway system and simulate the Yangon Circular Railway system to a greater extent. In the proposed software, we can easily visualize the train movement, modify the number of stations, the arrival rate, generate the simulation graph, modify the train, stations and speed, etc., to utilize the current resources.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122240677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparing BERT and XLNet from the Perspective of Computational Characteristics 从计算特性的角度比较BERT和XLNet
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051081
Hailong Li, Jaewan Choi, Sunjung Lee, Jung Ho Ahn
{"title":"Comparing BERT and XLNet from the Perspective of Computational Characteristics","authors":"Hailong Li, Jaewan Choi, Sunjung Lee, Jung Ho Ahn","doi":"10.1109/ICEIC49074.2020.9051081","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051081","url":null,"abstract":"Exploiting attention mechanism, Transformer provides superior performance compared to traditional CNN and RNN models on various NLP (Natural Language Processing) tasks. BERT and XLNet are two popular models utilizing Transformer. In this paper, we compare the computational characteristics of the inference of BERT and XLNet using MPRC (Microsoft Research Paraphrase Corpus), one of the popular language understanding benchmarks. Through evaluation, we observe that the both models exhibit similar computational characteristics except the target-position-aware representation and relative position encoding features of XLNet, leading to a better benchmark score at the cost of $mathit{1.2}times$ arithmetic operations and $mathit{1.5}times$ execution time on a modern CPU.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130705774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulation on Polishing Pad Wear in CMP Conditioning with Split Conditioner Disk 分离式调剂盘CMP调剂中抛光垫磨损的仿真研究
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051238
Hyunseop Lee
{"title":"Simulation on Polishing Pad Wear in CMP Conditioning with Split Conditioner Disk","authors":"Hyunseop Lee","doi":"10.1109/ICEIC49074.2020.9051238","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051238","url":null,"abstract":"Chemical mechanical polishing (CMP) is one of essential semiconductor fabrication processes to obtain highly integrated device. Many consumables are used in CMP process such as slurry, polishing pad, and diamond disk etc. Especially, the polishing pad determines the material removal rate (MRR) and its uniformity in CMP process. The CMP process requires pad conditioning to re-generate pad roughness; however, the conditioning with diamond disk results in pad wear. In this paper, authors proposed a novel CMP conditioning method with a split conditioner disk. According to numerical simulation, the analysis results show that the proposed split disk has lower pad wear rates and smoother wear profiles than commercial disk. Finally, it is likely that the proposed method can increase the lifetime of polishing pad in CMP process.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132544151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Acceleration of DNN Training Regularization: Dropout Accelerator DNN训练正则化的加速:Dropout加速器
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051194
Gunhee Lee, Hanmin Park, Soojung Ryu, Hyuk-Jae Lee
{"title":"Acceleration of DNN Training Regularization: Dropout Accelerator","authors":"Gunhee Lee, Hanmin Park, Soojung Ryu, Hyuk-Jae Lee","doi":"10.1109/ICEIC49074.2020.9051194","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051194","url":null,"abstract":"The training time of a deep neural network has increased such that training process may take many days or even weeks using a single device. Further, conventional devices such as CPU and GPU pursuit generality on their use, it is inevitable that they have drawbacks on energy efficiency for a specific use case such as DNN training. So accelerating DNN training is becoming an important part of DNN accelerator to achieve a high energy efficiency. This paper proposes an idea to save both execution time and DRAM energy consumption during DNN training by implementing dropout hardware efficiently. Simulation results show that our idea can save execution time and DRAM energy consumption on backward propagation as much as the dropped activations.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134388404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ticket Machine Queuing System Design Application for Service Efficiency Simulation and Comparison 售票机排队系统设计应用的服务效率仿真与比较
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051331
Suvit Poomrittigul, A. Koomsubsiri, Htain Lynn Aung, P. Sasithong, L. Wuttisittikulkij
{"title":"Ticket Machine Queuing System Design Application for Service Efficiency Simulation and Comparison","authors":"Suvit Poomrittigul, A. Koomsubsiri, Htain Lynn Aung, P. Sasithong, L. Wuttisittikulkij","doi":"10.1109/ICEIC49074.2020.9051331","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051331","url":null,"abstract":"This paper proposes the ticket machine queuing system design application in terms of service efficiency such as the average delay in queue and waiting time of the customer. This proposed application is applied in the queuing theory model and the observed main problem in rapid transit train system in Bangkok data for developing the application which can compare the service efficiency between existing system and desired system or new system that the operator would like to renew or improve the ticket machine system. The application can also be put on the adjustment parameter of service rate or number of the ticket machine, arrival rate of the system and designated position of queue or machine. We have extended the queuing model from previous report and analysis to make the ticket machine queuing system design application in graphical user interface by dragging and dropping the number of machines, position of machine and designated queue line for analysis and visualization in animation and graph analysis.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 30 Gb/s All-Digital CDR with a Phase Error Compensator 带相位误差补偿器的30gb /s全数字CDR
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051017
Kunhoo Park, Heejae Hwang, Jongsun Kim
{"title":"A 30 Gb/s All-Digital CDR with a Phase Error Compensator","authors":"Kunhoo Park, Heejae Hwang, Jongsun Kim","doi":"10.1109/ICEIC49074.2020.9051017","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051017","url":null,"abstract":"A 30 Gb/s all-digital clock and data recovery (CDR) circuit with a new phase error compensator is presented. The proposed phase error compensator removes the jitter component of the recovered clock that is unnecessarily increased by the error information generated by the samplers in the over-sampling CDRs. The proposed 30 Gb/s all-digital CDR is implemented in a 65-nm CMOS process and achieves a peak-to-peak recovered clock jitter of 5.09 ps. The proposed CDR dissipates 75 mW (=2.5 mW/Gbps) from a 1.2 supply","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121256451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Analysis of Factors Affecting Point Cloud Registration for Bin Picking 影响拣箱点云配准的因素分析
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051361
Jongwook Kim, Hyungmin Kim, Jong-Il Park
{"title":"An Analysis of Factors Affecting Point Cloud Registration for Bin Picking","authors":"Jongwook Kim, Hyungmin Kim, Jong-Il Park","doi":"10.1109/ICEIC49074.2020.9051361","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051361","url":null,"abstract":"The robotic bin picking system is commonly used to automate processes in the manufacturing industry, by estimating the six degree-of-freedom (6-DoF) pose of an object. In particular, in vision-based systems, the pose of an object is estimated by registering a 3D point cloud acquired from a computer-aided design (CAD) model with a 2.5D point cloud acquired from a depth map. The registration process requires the correspondence points between 3D point cloud and 2.5D point cloud. Unfortunately, since the 3D point cloud and the 2.5D point cloud have different dimensions, performing registration is more challenging than with equivalent dimensions. In this paper, therefore, we analyze the process of 3D point cloud to 2.5D point cloud registration through the experiments to perform stable bin picking task. For the experiments, 2.5D point cloud is synthesized from 3D CAD model and uniformly adjusted for density and depth noise. By registering 3D point cloud to adjusted 2.5D point cloud, we quantitatively analyze how the adjusted density and depth noise affect the registration process.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129304696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Memristor-Enabled Reconfigurable Integrated Circuits 忆阻器可重构集成电路
2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI: 10.1109/ICEIC49074.2020.9051041
Jakub Szypicyn, C. Papavassiliou, G. Papandroulidakis, G. Merrett, Alexander Serb, S. Stathopoulos, T. Prodromakis
{"title":"Memristor-Enabled Reconfigurable Integrated Circuits","authors":"Jakub Szypicyn, C. Papavassiliou, G. Papandroulidakis, G. Merrett, Alexander Serb, S. Stathopoulos, T. Prodromakis","doi":"10.1109/ICEIC49074.2020.9051041","DOIUrl":"https://doi.org/10.1109/ICEIC49074.2020.9051041","url":null,"abstract":"The holy grail of analogue integrated circuit design is adjustable analogue delay element. Of course, all analogue circuits are filters. Internal delays impose overall low-pass character to all circuits so that broadband amplifiers are lowpass filters, while high-pass amplifiers are in fact band-pass filters.","PeriodicalId":271345,"journal":{"name":"2020 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115657403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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