带相位误差补偿器的30gb /s全数字CDR

2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI:10.1109/ICEIC49074.2020.9051017

Kunhoo Park, Heejae Hwang, Jongsun Kim

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引用次数: 0

摘要

提出了一种带有相位误差补偿器的30gb /s全数字时钟和数据恢复电路。该相位误差补偿器消除了因过采样cdr中采样器产生的错误信息而不必要地增加的恢复时钟抖动分量。所提出的30 Gb/s全数字CDR采用65纳米CMOS工艺实现，峰值恢复时钟抖动为5.09 ps。所提出的CDR从1.2电源消耗75 mW (=2.5 mW/Gbps)

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A 30 Gb/s All-Digital CDR with a Phase Error Compensator

A 30 Gb/s all-digital clock and data recovery (CDR) circuit with a new phase error compensator is presented. The proposed phase error compensator removes the jitter component of the recovered clock that is unnecessarily increased by the error information generated by the samplers in the over-sampling CDRs. The proposed 30 Gb/s all-digital CDR is implemented in a 65-nm CMOS process and achieves a peak-to-peak recovered clock jitter of 5.09 ps. The proposed CDR dissipates 75 mW (=2.5 mW/Gbps) from a 1.2 supply

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2020 International Conference on Electronics, Information, and Communication (ICEIC)

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