A 30 Gb/s All-Digital CDR with a Phase Error Compensator

Abstract

A 30 Gb/s all-digital clock and data recovery (CDR) circuit with a new phase error compensator is presented. The proposed phase error compensator removes the jitter component of the recovered clock that is unnecessarily increased by the error information generated by the samplers in the over-sampling CDRs. The proposed 30 Gb/s all-digital CDR is implemented in a 65-nm CMOS process and achieves a peak-to-peak recovered clock jitter of 5.09 ps. The proposed CDR dissipates 75 mW (=2.5 mW/Gbps) from a 1.2 supply