2018 76th Device Research Conference (DRC)最新文献_第5页

A Vacuum Multi-Finger Transistor in CMOS Technology CMOS技术中的真空多指晶体管

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442158

S. Ghotbi, H. Pajouhi, S. Mohammadi

{"title":"A Vacuum Multi-Finger Transistor in CMOS Technology","authors":"S. Ghotbi, H. Pajouhi, S. Mohammadi","doi":"10.1109/DRC.2018.8442158","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442158","url":null,"abstract":"Electron filed emission is the process of emission of electrons from a conductor into the vacuum by means of an applied electric field and has a wide range of applications such as displays, electron guns, scanning electron microscopes, high power microwave amplifiers and micro- and nano-vacuum tubes. Vacuum electronic technology became obsolete by its poor reliability characteristics compared to semiconductor technologies. On the other hand, electrons in vacuum can accelerate to close to the speed of light, leading to potentially ultra-high speed devices if the gap between the emitting electrode (Cathode) and an opposing electrode (Anode) is very small (nanometer scale). In such nano-vacuum transistors [1]–[3], fabrication simplicity and reproducibility, high current density, good reliability characteristics and low cost fabrication are of prime importance. In this paper, a high density array of metallic nano-emitters are designed in a standard 45 nm CMOS technology, and are then post-processed using a simple one-step dry etching technology. No lithography is used in the post-CMOS fabrication. Field emission characteristics of the vacuum transistors have been measured. These devices show well-behaved transistor characteristics and are very promising for low-power high-speed applications.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ferroelectric Aluminum-Doped Hafnium Oxide for Memory Applications 用于存储的铁电铝掺杂氧化铪

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442244

Hojoon Ryu, Kai Xu, Ji Guo, Wenjuan Zhu

引用次数: 0

Optoelectronics based on Vertical Transport in Multi-layer MoS2 基于多层二硫化钼垂直输运的光电子学

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442171

Shubhadeep Bhattacharjee, Pranandita Biswas, Swanand V. Solanke, R. Muralidharan, D. Nath, N. Bhat

{"title":"Optoelectronics based on Vertical Transport in Multi-layer MoS2","authors":"Shubhadeep Bhattacharjee, Pranandita Biswas, Swanand V. Solanke, R. Muralidharan, D. Nath, N. Bhat","doi":"10.1109/DRC.2018.8442171","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442171","url":null,"abstract":"High photon absorption and photoconductive gain observed in 2D Transition Metal Dichalcogenides make them exciting candidates for high performance photodetectors and photovoltaics [1]. However, slow response times and low $mathrm{V}_{mathrm{oc}}$ (open circuit voltage) have hindered the development of reliable optoelectronic devices [1]. Most attempts to mitigate these disadvantages involve fabrication of complex heterostructures [2]–[4], which may render them unfit for large area production. Besides, almost all reports on MeSi-bascd opto-electronics exploit its lateral transport while studies on vertical transport towards detectors and photovoltaics are at an embryonic stage. In this work, we demonstrate that a facile vertical metal/multilaycr-Mo'Sc/rnctal device can be engineered to enable both excellent photodetectors (with high responsivity $> 3mathrm{A}/mathrm{W}$ & good speed ~ 1 ms) OR high $mathrm{V}_{mathrm{oc}}(sim 0.5mathrm{V})$ photovoltaics. We adopt a conscious design strategy of employing vertical instead of lateral transport through multilayer Mos2 as this provides both larger area for photon absorption, as well as short charge transfer length (enabling effective separation) [Fig l(a)].","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tunnel junctions for two-color nitride light emitting diodes and laser diodes grown by plasma assisted molecular beam epitaxy 等离子体辅助分子束外延生长的双色氮化发光二极管和激光二极管的隧道结

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442192

C. Skierbiszewski, H. Turski, M. Zak, K. Nowakowski-Szkudlarek, G. Muzioł, M. Siekacz, A. Feduniewicz-Żmuda, M. Sawicka

{"title":"Tunnel junctions for two-color nitride light emitting diodes and laser diodes grown by plasma assisted molecular beam epitaxy","authors":"C. Skierbiszewski, H. Turski, M. Zak, K. Nowakowski-Szkudlarek, G. Muzioł, M. Siekacz, A. Feduniewicz-Żmuda, M. Sawicka","doi":"10.1109/DRC.2018.8442192","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442192","url":null,"abstract":"One of the most challenging issues to address in nitride based devices like light emitting diodes (LEDs) and laser diodes (LDs) is poor conductivity of p-type region. Additionally, high resistance of the p-type contact, that is very difficult to reduce, determines performance and influences design of InGaN LEDs and LDs. Recently, there has been increasing attention given to the interband tunnel junctions (TJ) for effective carrier conversion between n-type and p-type material region in nitride LEDs and LDs. It was clearly demonstrated that TJ resistance for wide bandgap semiconductors can be effectively suppressed by making use of the piezoelectric fields in the region of the junction [1]. Low resistance TJ were investigated and realized using GaN/InGaN/GaN heterostructures. The MBE technology seems to be more efficient than MOVPE for practical realization of the devices with TJ. For MOVPE it is difficult to activate the p-type conductivity in the (In)GaN:Mg layers which are deeply buried below n-type layers due to the fact that diffusion of hydrogen is completely blocked through n-type layers. Therefore several attempts for hybrid MOVPE/MBE growth was performed and TJ LEDs [2], TJ LDs [3] and TJ VCSELs [4] were shown where active p-i-n region was grown by MOVPE and p-n TJ by MBE. However, the presence of the impurities in the MOVPE p-type surface used for MBE regrowth can deteriorate/limit performance of devices grown by hybrid method.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125130194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2D RF Electronics: from devices to circuits - challenges and applications 二维射频电子:从设备到电路-挑战和应用

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442190

D. Fadi, W. Wei, E. Pallecchi, M. Anderson, J. Stake, M. Deng, S. Frégonèse, T. Zimmer, H. Happy

{"title":"2D RF Electronics: from devices to circuits - challenges and applications","authors":"D. Fadi, W. Wei, E. Pallecchi, M. Anderson, J. Stake, M. Deng, S. Frégonèse, T. Zimmer, H. Happy","doi":"10.1109/DRC.2018.8442190","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442190","url":null,"abstract":"We developed process technologies dedicated to high frequency graphene field-effect transistors (GFETs). We used graphene from different sources (graphene growth directly on silicon carbide (SiC) substrate by chemical vapor deposition (CVD) technique [1], CVD graphene growth on Cu foil and transferred on Si02/Si substrate [2]) to realize two GFET structures (top gate and back gate transistors). After fabrication, we have explored the high frequency performances of GFETs including noise performances. The performances of GFET achieved are comparable to the state of the art with the gate length. The noise parameters of the transistors are mandatory for circuit design (linear application such as amplifier). These parameters limit the performances of the device when small signals are considered. The effort was made here to measure the noise parameters of GFET $(mathrm{NF}_{min}, mathrm{R}_{mathrm{n}}, Gamma_{mathrm{opt}})$. It is well known that these parameters depend both on intrinsic properties of the graphene material (noise generated in the channel under the gate), as well as extrinsic parameters related to the technological process (mainly noise generated by access resistances, …). Based on the reliability of the process, RF circuits were designed and fabricated. These circuits demonstrated the potential to achieve high performances in the field of linear circuit such as amplifiers, and non-linear circuits such as mixers.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122554297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Quantifying the thermal boundary conductance of 2D-substrate interfaces 二维基板界面热边界电导的量化

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442183

C. Foss, Z. Akšamija

引用次数: 0

Room temperature resonant tunneling in metal-insulator-insulator-insulator-semiconductor devices 金属-绝缘体-绝缘体-绝缘体-半导体器件的室温共振隧穿

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/drc.2018.8442151

J. Reyes, H. Uribe-Vargas

引用次数: 0

Experimental Investigation of N-Channel Oxygen-Inserted (OI) Silicon Channel MOSFETs with High-K/Metal Gate Stack 高k /金属栅极堆n沟道含氧硅沟道mosfet的实验研究

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442231

Jeffrey A. Smith, H. Takeuchi, R. Stephenson, Yi-Ann Chen, M. Hytha, R. Mears, S. Datta

引用次数: 5

CMOS 3D-Extended Metal Gate ISFETs with Near Nernstian Ion Sensitivity 具有近能态离子灵敏度的CMOS 3d扩展金属栅极isfet

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442197

Junrui Zhang, F. Bellando, M. Rupakula, E. G. Cordero, N. Ebejer, J. Longo, F. Wildhaber, H. Guérin, A. Ionescu

{"title":"CMOS 3D-Extended Metal Gate ISFETs with Near Nernstian Ion Sensitivity","authors":"Junrui Zhang, F. Bellando, M. Rupakula, E. G. Cordero, N. Ebejer, J. Longo, F. Wildhaber, H. Guérin, A. Ionescu","doi":"10.1109/DRC.2018.8442197","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442197","url":null,"abstract":"Over the past few decades, Ion Sensitive Field Effect Transistor (ISFET) has been fabricated using a variety of technologies [1] based on the idea of an ion-sensitive gate. In the effort to bring ISFETs into Point-of-Care applications and wearable products [2], their compatibility with industrial CMOS processes is crucial for realizing miniaturized integrated sensor system. The challenges are high, knowing that it is very difficult to change any processing steps in established CMOS Front-End-of-the-Line. Moreover, the majority of ISFETs fabricated in commercial CMOS processes and reported to date showed low sensitivity, especially when using oxynitrides as sensing gate insulator [3]. In this work, we report for the first time, to the best of our knowledge, a post-processed $0.18 mu mathrm{m}$ commercial CMOS chip where the transducing transistor and the sensing gate electrode are vertically co-integrated, resulting a 3D-Extended Metal Gate ISFET (3D-EMG-ISFET). The top electrode is made of Al with an Al2O3 native oxide connected to the transistor gate by using vertical vias. With this approach, a sensitivity of 56.8 mV/pH is achieved. The proposed ISFET is validated as a full-scale pH sensor and it can be fabricated in a non-modified commercial CMOS process.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132110704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Neuromorphic and Quantum Devices 神经形态和量子器件

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/drc.2018.8443299

引用次数: 0