2018 76th Device Research Conference (DRC)最新文献_第4页

Nanoscale Scanning Probe Thermometry of TaOe-based selector devices 基于陶陶选择器的纳米扫描探针测温

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442146

Dasheng Li, G. Ramer, Phoebe Yeoh, B. Hoskins, Yuanzhi Ma, J. Bain, A. Centrone, M. Skowronski

{"title":"Nanoscale Scanning Probe Thermometry of TaOe-based selector devices","authors":"Dasheng Li, G. Ramer, Phoebe Yeoh, B. Hoskins, Yuanzhi Ma, J. Bain, A. Centrone, M. Skowronski","doi":"10.1109/DRC.2018.8442146","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442146","url":null,"abstract":"Crosspoint memory arrays suffer from the sneak path problem, which may cause read failures and increase power consumption [1]. The high nonlinearity of threshold switching devices makes them an ideal candidate for selector device to suppress the leakage current in the one selector/one resistor architecture. However, the mechanism of threshold switching, in particular Negative Differential Resistance (NDR) behavior in oxide materials such as TaOx and NlrO; is still under debate. A leading hypothesis is Joule-heating-induced thermal runaway [2] producing NDR due to spontaneous current localization within the device region. So far, there is no experimental data on the size of the constriction and the temperature within it. We demonstrate the first use of scanning thermal microscopy (SThM) and scanning joule heating expansion microscopy (SJEM), two AFM-based high spatial resolution in-situ characterization methods to directly measure the temperature distribution up to the NDR region in TaOx-based selector devices. These experimental results are essential information for developing accurate numerical modeling of threshold switching devices.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Insinhts on the DC Characterization of Ferroelectric Field-Effect-Transistors 铁电场效应晶体管直流特性研究进展

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442191

M. Jerry, Jeffrey A. Smith, K. Ni, A. Saha, S. Gupta, S. Datta

{"title":"Insinhts on the DC Characterization of Ferroelectric Field-Effect-Transistors","authors":"M. Jerry, Jeffrey A. Smith, K. Ni, A. Saha, S. Gupta, S. Datta","doi":"10.1109/DRC.2018.8442191","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442191","url":null,"abstract":"In this work, we report on the fabrication, characterization, and modeling of ferroelectric field-effect- transistors (FeFET). We demonstrate that polarization switching within ordinary 1T ferroelectric memory devices under specific conditions results in the measurement of subthreshold slopes $< 2.3mathrm{kT}/mathrm{q}$, near-zero hysteresis, negative drain induced barrier lowering (N-DIBL), and negative differential resistance (NDR) (Fig. 1). The polarization switching origin is identified by a strong dependence on the magnitude of the gate voltage, where below the critical gate voltage required to switch polarization, $mathrm{SS} < 2.3mathrm{kT}/mathrm{q}$, near-zero hysteresis, and negative DIBL cannot be observed. Further, we identify the source of NDR in the output characteristics to result from polarization switching near the drain of the FeFET at 10w $mathrm{V}_{mathrm{GS}}$ and high $mathrm{V}_{mathrm{DS}}$. The NDR can be reproduced by a simple analytical model where two VT are present within the FeFET channel due to a non-uniform distribution of the polarization charge along the channel length. The intent of this work is to disambiguate and draw distinction between the effects of polarization switching in FeFET memory devices from that of negative capacitance as shown in Kwon et. al. [1], where a physically thicker oxide shows all the electric nronerties of a nhvsicallv thinner dielectric.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133917867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Paper electronics: a sustainable multifunctional platform 纸电子:一个可持续的多功能平台

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442238

E. Fortunato, D. Gaspar, Inês Cunha, M. Mendes, A. Vicente, H. Águas, A. Marques, A. Pimentel, D. Nunes, Luís Pereira, R. Martins

引用次数: 0

Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory 一种完全硅兼容的免成形电阻开关随机存取存储器的制造与表征

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442248

Jae Yoon Lee, Youngmin Kim, Ikhyeon Kworn, I. Cho, Jae Yeon Lee, S. Kim, Seongjae Cho

引用次数: 0

Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters 缩放FinFET和NSFET CMOS逆变器的有效驱动电流

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442220

A. Razavieh, Y. Deng, P. Zeitzoff, M. Na, J. Frougier, G. Karve, D. Brown, T. Yamashita, E. Nowak

引用次数: 10

Manufacturable Heterogeneous Integration for Flexible CMOS Electronics 柔性CMOS电子器件的可制造异构集成

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442163

M. Hussain, S. Shaikh, G. T. Sevilla, J. M. Nassar, A. Hussain, R. Bahabry, S. Khan, A. Kutbee, J. Rojas, M. Ghoneim, M. Cruz

{"title":"Manufacturable Heterogeneous Integration for Flexible CMOS Electronics","authors":"M. Hussain, S. Shaikh, G. T. Sevilla, J. M. Nassar, A. Hussain, R. Bahabry, S. Khan, A. Kutbee, J. Rojas, M. Ghoneim, M. Cruz","doi":"10.1109/DRC.2018.8442163","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442163","url":null,"abstract":"Nearly sixty years back when Jack Kilby built the first integrated circuit (IC), it was also the beginning of today's advanced and matured complementary metal oxide semiconductor (CMOS) technology whose arts and science of miniaturization has enabled Moore's Law to double up the number of devices in a given area in every two years. It has also been possible because CMOS technology has consistently adopted new materials and processes. High performance (data processing speed in computational devices), energy efficiency (for portable devices) and ultra-large-scale-integration (ULSI) density - all these features have been added to every major technology generation in additive manner. As we go forward and embrace Internet of Everything (IoE) where people, process, device and data are going to be seamlessly connected, we may want to ask ourselves a few fundamental questions about the future of CMOS electronics, enabling role of CMOS technology, potential benefits and application opportunities. Physically flexible electronics are increasingly getting attention as a critical and impactful expansion area for the general area of electronics. Many exciting demonstrations have been made to point out to its powerful prospect. Due to the paradox that traditional crystalline materials based electronics are useful in data management but they are naturally rigid and bulky, most of the researchers have resorted to two strategies: (i) non-silicon based fully flexible system with limited functionality and (ii) hybrid flexible electronic system with off-the-shelf ICs for data management. We do not consider this paradox is fundamental and a block-by-block approach using traditional CMOS technology can allow us to build fully flexible CMOS electronic systems [Fig. 1].","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129711220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Three-Dimensionally Structured Betavoltaics 三维结构贝塔光伏

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442157

John W. Murphy, C. Frye, Fang Qian, J. Despotopulos, R. Henderson, Q. Shao, K. Kazkaz, L. Voss, R. Nikolic

引用次数: 0

Thickness Tunable Transport Properties in $mathbf{MoTe}_{mathbf{2}}$ Field Effect Transistors $mathbf{MoTe}_{mathbf{2}}$场效应晶体管的厚度可调输运特性

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442261

Yuqi Zhu, Feng Zhang, J. Appenzeller

引用次数: 0

High Voltage Vertical Gallium Nitride Pseudo-Junction-Barrier-Schottky Diode with Ion Implantation 离子注入的高压垂直氮化镓赝结势垒肖特基二极管

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442214

Sizhen Wang, A. Huang

引用次数: 0

Cockcroft-Walton Multiplier based on Unipolar $mathbf{Ag/HfO_{2}/Pt}$ Threshold Switch 基于单极$mathbf{Ag/HfO_{2}/Pt}$阈值开关的Cockcroft-Walton乘法器

2018 76th Device Research Conference (DRC) Pub Date : 2018-06-01 DOI: 10.1109/DRC.2018.8442270

A. Aziz, N. Shukla, A. Seabaugh, S. Datta, S. Gupta

引用次数: 0