2009 22nd International Conference on VLSI Design最新文献_第8页

New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets 加速小延迟ATPG和生成紧凑测试集的新技术

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.64

Boxue Yin, D. Xiang, Zhen Chen

引用次数: 7

Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at India 微电子领域的教育、研究和工业基础设施——全球展望和印度展望

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.17

B. Courtois, K. Torki, S. Dumont, S. Eyraud, J.-F. Paillotin, G. D. Pendina

引用次数: 0

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL 专用重写:RTL中低功耗转换的自动验证

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.85

V. Viswanath, Shobha Vasudevan, J. Abraham

引用次数: 7

Why is Design Automation and Reuse of Analog Designs Increasingly Trailing the Digital World? 为什么模拟设计的设计自动化和重用越来越落后于数字世界?

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.107

G. Agarwal, Prakash Bare

引用次数: 0

Efficient Implementation of Floating-Point Reciprocator on FPGA 浮点往复器在FPGA上的高效实现

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.12

M. Jaiswal, N. Chandrachoodan

引用次数: 6

Exploring the Limits of Port Reduction in Centralized Register Files 中心化寄存器文件端口缩减的极限探索

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.29

Sandeep Sirsi, Aneesh Aggarwal

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引用次数: 4

ReConfigurable Technologies 可重构技术

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.123

Mona Mathur

引用次数: 7

An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis 用静态时序分析测量动态电压波动对性能影响的方法

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.45

Ramamurthy Vishweshwara, R. Venkatraman, H. Udayakumar, N. Arvind

{"title":"An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis","authors":"Ramamurthy Vishweshwara, R. Venkatraman, H. Udayakumar, N. Arvind","doi":"10.1109/VLSI.Design.2009.45","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.45","url":null,"abstract":"Design closure for predictable silicon performance is emerging as the most challenging digital VLSI design problem in advanced deep-submicron technology nodes. One of the significant problems is effective power-grid distribution,and the comprehension of the impact of voltage drops in the power grid on design timing and performance. This paper proposes a way by which the complex interactions between timing and dynamic power drops can be comprehended without being significantly pessimistic, while also not losing out on accuracy. We highlight the heuristics that we have used in this regard to reduce the complexity of the timing analysis, and to reduce the overall computation time. The overall method uses conventional analysis approaches for dynamic voltage-drop and timing. This method proposes options for comprehending effects of dynamic voltage drops during traditional design-closure methods and also highlights means of validating any assumptions made. Comparison results between performance degradation due to voltage drop assumptions and the traditional margin based approaches show significant reduction in the pessimism and these are presented in this paper.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129281779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study 使用商品图形硬件加速系统级设计任务:一个案例研究

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.35

Unmesh D. Bordoloi, S. Chakraborty

{"title":"Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study","authors":"Unmesh D. Bordoloi, S. Chakraborty","doi":"10.1109/VLSI.Design.2009.35","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.35","url":null,"abstract":"Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-hard). As a result, they involve high running times even for mid-sized problems. In this paper we explore the possibility of using commodity graphics processing units (GPUs) to accelerate such tasks that commonly arise in the electronic design automation (EDA) domain. We demonstrate this idea via a detailed case study on a general hardware/software design space exploration problem and propose a GPU-based engine for it. Not only does this problem commonly arise in the embedded systems domain, its computational kernel turns out to be a general combinatorial optimization problem (viz. the knapsack problem) which lies at the heart of several EDA applications. Our experimental results show that our GPU-based implementation offers very attractive speedups for this computational kernel (up to 100×), and speedups of up to 17× for the full problem. In contrast to ASIC/FPGA-based accelerators – since even low-end desktop and notebook computers are today equipped with GPUs – our solution involves no extra hardware cost. Although recent research has shown the benefits of using GPUs for a variety of non-graphics applications (e.g. in databases and bioinformatics), hardly any work has been done on harnessing the parallelism of GPUs to accelerate problems from the EDA domain. We hope that our results and the generality of the problem we address will motivate researchers from this community to explore the possibility of using GPUs for a wider variety of problems from the EDA domain.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124196174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel 同时路由和馈通算法减少顶部信道的拥塞

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.83

S. Prasad, Anuj Kumar

引用次数: 0