Efficient Implementation of Floating-Point Reciprocator on FPGA

Abstract

In this paper we have presented an efficient FPGA implementation of a  reciprocator for both IEEE single-precision and double-precision  floating point numbers. The method is based on the use of look-up tables and partial block multipliers. Compared with previously reported work, the modules occupy less area with a higher performance and less latency. The designs trade off either 1 unit in last-place (ulp) or 2 ulp of accuracy (for double or single precision respectively), without rounding, to obtain a better implementation. Rounding can also be added to the design to restore some accuracy at a slight cost in area.