2009 22nd International Conference on VLSI Design最新文献_第10页

Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design 自动化模拟电路设计中基于模糊逻辑的图语法框架指导

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.79

Angan Das, R. Vemuri

引用次数: 5

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions 大型复杂SoC设计中的优化质量评估挑战与解决方案

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.52

R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, M. Rao, J. Rao

引用次数: 2

An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays 考虑门延迟影响的多攻击者串扰故障的基于ILP的ATPG技术

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.10

Kunal P. Ganeshpure, S. Kundu

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引用次数: 3

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection 一种7T/14T可靠SRAM及其避免半选择的阵列结构

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.54

H. Fujiwara, S. Okumura, Y. Iguchi, Hiroki Noguchi, H. Kawaguchi, M. Yoshimoto

引用次数: 23

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems 实时嵌入式系统的调度感知缓存重构

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.66

Weixun Wang, P. Mishra, A. Gordon-Ross

引用次数: 21

Encoding of Floorplans through Deterministic Perturbation 基于确定性扰动的平面图编码

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.49

Debasri Saha, S. Sur-Kolay

引用次数: 4

Design of a Low Power, Variable-Resolution Flash ADC 一种低功耗、可变分辨率闪存ADC的设计

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-05 DOI: 10.1109/VLSI.Design.2009.62

S. Veeramachaneni, M. K. Adimulam, V. Tummala, M. Srinivas

引用次数: 28

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems 用于低vdd高速嵌入式系统的单端静态随机存取存储器

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-01 DOI: 10.1109/VLSI.Design.2009.38

Jawar Singh, J. Mathew, S. Mohanty, D. Pradhan

引用次数: 7

A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link 2.4Gbps-4.8Gbps XDR-DRAM io链路

2009 22nd International Conference on VLSI Design Pub Date : 2009-01-01 DOI: 10.1109/VLSI.Design.2009.65

Vijay Khawshe, K. Vyas, Renu Rangnekar, Prateek Goyal, V. Krishna, K. Prabhu, P. Venkatesan, L. Raghavan, Rajkumar Palwai, M. Thrivikraman, K. Desai, Abhijit Abhyankar

{"title":"A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link","authors":"Vijay Khawshe, K. Vyas, Renu Rangnekar, Prateek Goyal, V. Krishna, K. Prabhu, P. Venkatesan, L. Raghavan, Rajkumar Palwai, M. Thrivikraman, K. Desai, Abhijit Abhyankar","doi":"10.1109/VLSI.Design.2009.65","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.65","url":null,"abstract":"This paper focuses on the design of a 2.4Gbps to 4.8Gbps link developed in TSMC65nmG+ technology, for the high speed and high throughput interface between XDR™ (Extreme data rate) DRAM and ASIC. Applications such as HDTV and high end graphics require high bandwidth interface between controllers and memory. This XDR I/O (XIO) link which is integrated in the controller, interfaces with the XDR™ DRAM and provides the very high per pin bandwidth. To maintain a constant transmit swing the link supports automatic calibration for the on-die termination (ODT) and driver circuit bias. The channel timing between, ASIC pin to XDR-DRAM pin, is calibrated for all the individual pins to de-skew any channel electrical timing differences to align the data transfer during Memory Read and Writes. This calibration is done periodically to maintain constant timing margin throughout the operation. The self biased [1] regulated PLL dual loop architecture based on [2] is used which minimizes the clock jitter and enables high speed operation. A novel programmable Voltage Control Oscillator is used here to work at wide range of frequencies. The cell with 8bit wide data bus and 16bit wide command bus, consumes 520mW at 4.0Gbps.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133697786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

EDA Made-in-India: Fact or Fiction? EDA印度制造:事实还是虚构?

2009 22nd International Conference on VLSI Design Pub Date : 1900-01-01 DOI: 10.1109/VLSI.Design.2009.108

Raman Santhanakrishnan, Y. Trivedi

引用次数: 0