Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions

Design optimisation of large system-on-chip (SoC) designs presents significant challenges in terms of the number of care-abouts in today's chip design scenario. While optimisation approaches have focused on key aspects like design timing, power and routability, there are several critical aspects that do not get modelled by the abstraction approaches used in current solutions, resulting in local areas of potentially bad quality of results (QoR). The definition of design quality metrics for assessing various aspects of interest thus comes out as a key requirement in designs today. In this paper, we highlight the key challenges in the design of large, complex SoCs and propose some design metrics that identify problem areas for improvement. We highlight how conventional abstraction schemes tend to mask such problems when looking at design-level averaging for the relevant cost-functions. We present the results of these metrics and also show why not resolving some of these potential bottle-necks could lead to significant challenges in overall design closure.