2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)最新文献

Reinforcement Learning based Efficient Mapping of DNN Models onto Accelerators 基于强化学习的DNN模型到加速器的高效映射

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772673

Shine Parekkadan Sunny, Satyajit Das

{"title":"Reinforcement Learning based Efficient Mapping of DNN Models onto Accelerators","authors":"Shine Parekkadan Sunny, Satyajit Das","doi":"10.1109/coolchips54332.2022.9772673","DOIUrl":"https://doi.org/10.1109/coolchips54332.2022.9772673","url":null,"abstract":"The input tensors in each layer of Deep Neural Network (DNN) models are often partitioned/tiled to get accommodated in the limited on-chip memory of accelerators. Studies show that efficient tiling schedules (commonly referred to as mapping) for a given accelerator and DNN model reduce the data movement between the accelerator and different levels of the memory hierarchy improving the performance. However, finding layer-wise optimum mapping for a target architecture with a given energy and latency envelope is an open problem due to the huge search space in the mappings. In this paper, we propose a Reinforcement Learning (RL) based automated mapping approach to find optimum schedules of DNN layers for a given architecture model without violating the specified energy and latency constraints. The learned policies easily adapt to a wide range of DNN models with different hardware configurations, facilitating transfer learning improving the training time. Experiments show that the proposed work improves latency and energy consumption by an average of 21.5% and 15.6% respectively compared to the state-of-the-art genetic algorithm-based GAMMA approach for a wide range of DNN models running on NVIDIA Deep Learning Accelerator (NVDLA). The training time of RL-based transfer learning is 15× faster than that of GAMMA.","PeriodicalId":266152,"journal":{"name":"2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127722938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Encoder-based Many-Pattern Matching on FPGAs 基于编码器的fpga多模式匹配

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772671

H. Vu, Ngoc-Dai Bui

{"title":"Encoder-based Many-Pattern Matching on FPGAs","authors":"H. Vu, Ngoc-Dai Bui","doi":"10.1109/coolchips54332.2022.9772671","DOIUrl":"https://doi.org/10.1109/coolchips54332.2022.9772671","url":null,"abstract":"Many-pattern matching is one of the most essential algorithms in many application domains, such as data mining, network security, and bioinformatics. Such high-throughput application domains require high-performance matching engines, leading to the deployment of the algorithm on hardware. However, such hardware deployment consumes a large number of hardware resources. This challenge becomes more critical when scaling the number of patterns as well as the data throughput. In this paper, we first proposed an encoder-based hardware architecture for many-pattern matching on FPGAs. The matching architecture includes two parts: encoder-based filter and matching block. We also proposed an algorithm to simplify the structure of the encoder-based filter, thus reducing the hardware utilization. The hardware architecture is scalable with the number of patterns and the input data throughput. We evaluated our matching architecture and our algorithm with 2048 32-byte patterns abstracted from Snort rules for malware. The evaluation on Xilinx Zedboard shows that at 2.16 Gbps throughput, the proposed architecture achieves higher hardware efficiency at 0.05 LUTs per character, a block RAM consumption 10% of total device, and almost no flip-flop consumption, while the maximum clock frequency and the latency are 270 MHz and 11 ns, respectively.","PeriodicalId":266152,"journal":{"name":"2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128818076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications 用于TinyML应用的1036 TOp/s/W、12.2 mW、2.72 μJ/Inference全数字TNN加速器

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772668

Moritz Scherer, Alfio Di Mauro, Georg Rutishauser, Tim Fischer, L. Benini

引用次数: 6

Body Bias Control on a CGRA based on Convex Optimization 基于凸优化的CGRA车身偏置控制

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772708

Takuya Kojima, Hayate Okuhara, Masaaki Kondo, H. Amano

引用次数: 0

Session III Panel Discussions: The Future of Mission-critical, Mixed-criticality High-performance Embedded Systems 第三部分小组讨论:关键任务、混合关键高性能嵌入式系统的未来

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772707

引用次数: 0

A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms 移动平台上具有密集RGB-D数据采集的低功耗实时三维目标识别处理器

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772667

Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, H. Yoo

引用次数: 0

DXT501:An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless Communication DXT501:基于sdr的多协议工业无线通信基带MP-SoC

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772697

Yang Chen, Lin Liu, Xuelin Feng, Jinglin Shi

引用次数: 0

A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training 具有电路非线性感知训练的记忆电容尖峰神经网络

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772674

Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Y. Nakashima

{"title":"A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training","authors":"Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Y. Nakashima","doi":"10.1109/coolchips54332.2022.9772674","DOIUrl":"https://doi.org/10.1109/coolchips54332.2022.9772674","url":null,"abstract":"Neuromorphic computing is an unconventional computing scheme that executes computable algorithms using Spiking Neural Networks (SNNs) mimicking neural dynamics with high speed and low power consumption by the dedicated hardware. The analog implementation of neuromorphic computing has been studied in the field of edge computing etc. and is considered to be superior to the digital implementation in terms of power consumption. Furthermore, It is expected to have extremely low power consumption that Processing-In-Memory (PIM) based synaptic operations using non-volatile memory (NVM) devices for both weight memory and multiply-accumulate operations. However, unintended non-linearities and hysteresis occur when attempting to implement analog spiking neuron circuits as simply as possible. As a result, it is thought to cause accuracy loss when inference is performed by mapping the weight parameters of the SNNs which trained offline to the element parameters of the NVM. In this study, we newly designed neuromorphic hardware operating at 100 MHz that employs memcapacitor as a synaptic element, which is expected to have ultra-low power consumption. We also propose a method for training SNNs that incorporate the nonlinearity of the designed circuit into the neuron model and convert the synaptic weights into circuit element parameters. The proposed training method can reduce the degradation of accuracy even for very simple neuron circuits. The proposed circuit and method classify MNIST with ∼33.88 nJ/Inference, excluding the encoder, with ∼97% accuracy. The circuit design and measurement of circuit characteristics were performed in Rohm 180nm process using HSPICE. A spiking neuron model that incorporates circuit non-linearity as an activation function was implemented in PyTorch, a machine learning framework for Python.","PeriodicalId":266152,"journal":{"name":"2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131489833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Power Analysis of Directly-connected FPGA Clusters 直连FPGA集群的功耗分析

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772675

Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, H. Amano

引用次数: 0

Hardware Acceleration of Aggregate Signature Generation and Authentication by BLS Signature over BLS12-381 curve BLS12-381曲线上BLS签名聚合签名生成和认证的硬件加速

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) Pub Date : 2022-04-20 DOI: 10.1109/coolchips54332.2022.9772706

Kaoru Masada, R. Nakayama, M. Ikeda

引用次数: 2