{"title":"Ultra-low Latency 8K Video-transmission System Utilizing Disaggregation Configuration","authors":"Yasuhiro Mochida, D. Shirai, K. Takasugi","doi":"10.1109/coolchips54332.2022.9772705","DOIUrl":"https://doi.org/10.1109/coolchips54332.2022.9772705","url":null,"abstract":"We present a first-ever video-transmission system for remote production capable of sending and receiving uncompressed 8K video in the SMPTE ST 2110 directly through optical paths. To increase the robustness, a transmitter buffer control in seamless protection switching is also presented. We implemented video-transmission functions on an optical transponder utilizing disaggregation configuration. An evaluation experiment demonstrated that our video-transmission system achieved a delay of less than 1 ms between the video input at the transmitting end and video output at the receiving end.","PeriodicalId":266152,"journal":{"name":"2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130722063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nakamura, Yuya Omori, Daisuke Kobayashi, K. Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
{"title":"An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture","authors":"K. Nakamura, Yuya Omori, Daisuke Kobayashi, K. Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi","doi":"10.1109/coolchips54332.2022.9772670","DOIUrl":"https://doi.org/10.1109/coolchips54332.2022.9772670","url":null,"abstract":"Video coding hardware is essential for various video applications, and to meet demands for higher resolution, the parallel video encoding architecture is often adopted, in which reference images are shared among encoder modules to maintain coding efficiency. However, conventional sharing methods are not always efficient in utilization of transferred image data. In this paper, we propose a method to reduce the amount of data transfer efficiently by using both pre-transfer and on-demand transfer. Experimental results show that the data transfer can be reduced to 19.8-35.3% of the conventional method on average although the access error rate increases to 0.5-2%. This makes it possible to reduce the required bandwidth of the inter-chip interface by saving the amount of data transfer.","PeriodicalId":266152,"journal":{"name":"2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129907398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, H. Ochi
{"title":"Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations","authors":"Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, H. Ochi","doi":"10.1109/coolchips54332.2022.9772704","DOIUrl":"https://doi.org/10.1109/coolchips54332.2022.9772704","url":null,"abstract":"A standard cell memory (SCM) is a memory constructed with standard cells and implemented by logic synthesis and automatic placement and routing, which enables stable operation in the low voltage region compared to an SRAM. In this paper, we show the measurement results of a nonvolatile SCM (NV-SCM) using a Fishbone-in-Cage Capacitor (FiCC), which is suitable for IoT processors with intermittent operations. The NV-SCM was fabricated in a 180 nm standard CMOS process technology. The area overhead from the nonvolatility of bit cells is 74%. We confirmed full functionality of the NV-SCM. In the normal read/write and the data restore operation, the NV-SCM can operate up to 21 MHz. The data retention time was 95 minutes when the write time to the nonvolatile memory was 0.3 seconds and the reading voltage was set to 1.4 V. The simulation results show that the proposed NV-SCM can reduce the energy consumption by 51.19% compared to a conventional volatile SCM when hybernation/normal operation time ratio is 500.","PeriodicalId":266152,"journal":{"name":"2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124387637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}