O. Patterson, R. Hafer, S. Mittal, Ankur Arya, K. Stein, H. Ho, William Davies, Xiaohu Tang, Brian Yueh-Ling Hsieh, Shuen-Cheng Chris Lei
{"title":"In-line characterization of EDRAM for a FINFET technology using VC inspection","authors":"O. Patterson, R. Hafer, S. Mittal, Ankur Arya, K. Stein, H. Ho, William Davies, Xiaohu Tang, Brian Yueh-Ling Hsieh, Shuen-Cheng Chris Lei","doi":"10.1109/ASMC.2016.7491150","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491150","url":null,"abstract":"An E-beam voltage contrast inspection methodology involving multiple inspection points has been created to support development of the EDRAM module for a recent FINFET technology. This methodology provides within-sector feedback for a wide range of defect types enabling fast turn-around of split experiments and early detection of process excursions. Most defectivity affecting EDRAM is buried and therefore not detectable with broad beam plasma inspection. The EDRAM module is first in the process sequence for this FINFET technology. Without E-beam inspection, the first opportunity for defectivity feedback would be metal 1 test, which is months later in the process sequence. While direct E-beam inspection of functional EDRAM is a key part of this methodology, many defect types cannot be detected directly on functional SRAM. Special voltage contrast test structures were designed to monitor these defect types. The key defect types and the strategy used to detect each of them is described in detail in this paper. Select split experiment and process excursion data are used to illustrate the impact of the methodology.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"7 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nitin Garg, Philippe Helal, P. Muralidhar, S. Crown, Vincent Sih, S. Waite, Silas Scott
{"title":"Yield improvement and queue time relaxation at contact process","authors":"Nitin Garg, Philippe Helal, P. Muralidhar, S. Crown, Vincent Sih, S. Waite, Silas Scott","doi":"10.1109/ASMC.2016.7491163","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491163","url":null,"abstract":"As dimension shrinks in advanced technology nodes, the critical dimension (CD) plays a critical role and so does QTime. Front Opening Unified Pod (FOUP) door closure, delaying FOUP door opening, introducing N2 Purge and creating vacuum at optimum steps and for optimized duration has shown promising results in extending QTime and improving yield. Etch is often performed by reactive ion etching (RIE) process which generally has a physical and a chemical component to it. Etch residues, sometimes polymeric with metallic contaminants embedded inside, have to be removed in timely manner. If post etch residue (PER) is not removed soon enough, this gas/polymer then interacts with moisture inside the FOUP, leading to footing at the Nitride Stress layer and crystal growth on patterned wafers — thereby degrading yield. In this paper, we will discuss various approaches taken to improve the footing at bottom of contacts and increase the Queue Time (QTime) between Etch and Cleans processes.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Robert Schmaler, C. Hammel, T. Schmidt, Matthias Schöps
{"title":"Dispatching rules considering transport-related restrictions during failure scenarios — A use case: FA: Factory automation","authors":"Robert Schmaler, C. Hammel, T. Schmidt, Matthias Schöps","doi":"10.1109/ASMC.2016.7491110","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491110","url":null,"abstract":"Integration of transport system information into Manufacturing Execution System (MES) dispatching rules is not yet standard practice. Yet, it could be helpful in several areas of a semiconductor fabrication plant. For example, to react to system failures. Even in fully-automated manufacturing facilities, the MES dispatches production material with consideration of tool utilization and lowest cycle-time. Transport-related restrictions are not reflected in the dispatching rules. The new system logic presented in this paper (called Vehicle Area Controller - VAC) proposes to overcome this limitation, and presents an initial example, which shows that this combination has the potential to minimize throughput loss for production, during AMHS failure scenarios.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131577184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improvement of hydrogen detection limit for quadruple SIMS tool","authors":"Z. Zhang, B. Hengstebeck, F. Stevie, M. Hopstaken","doi":"10.1109/ASMC.2016.7491119","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491119","url":null,"abstract":"Hydrogen is an element of significant interest for semiconductor process; however it cannot be detected by many available elemental analysis techniques. Secondary ion mass spectrometry (SIMS) is one of the few techniques for the measurement of hydrogen amount and depth distribution. Among all kinds of SIMS tools, magnetic sector, quadrupole and time-of-flight, quadrupole SIMS instrument usually has lowest vacuum pressure and therefore should have better hydrogen detection limit. But high blast-through noise from mass 0 to mass 1 significantly affects the hydrogen detection limit. Various methods to improve hydrogen detection limit were investigated in this study. With field axis potential bias and higher mass edge measurement, hydrogen detection limit of quadrupole SIMS tool was improved by one order of magnitude to 2.2×1018 atoms/cm3.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115396429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Rajagopalan, J. Laloe, M. Silvestre, E. Ramanathan, Sohana Khanal, Alain Laval, Q. Ge, N. Takahashi, A. S. Mahalingam, S. L. Liew, Robert Teagle
{"title":"Extra-pattern killer defectivity improvement and enhancement of within-feature barrier coverage by optimization of TaN barrier PVD process in 90p Cu wire interconnects for 28nm technology","authors":"B. Rajagopalan, J. Laloe, M. Silvestre, E. Ramanathan, Sohana Khanal, Alain Laval, Q. Ge, N. Takahashi, A. S. Mahalingam, S. L. Liew, Robert Teagle","doi":"10.1109/ASMC.2016.7491165","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491165","url":null,"abstract":"The BEOL Barrier-Seed deposition process is a key component in achieving the desired electrical and electro-migration performance while balancing the step coverage. The process also has a multifold impact on wafer yield parametric since it serves multiple passes for the various metal levels. Two major challenges with the barrier sputter deposition are: (A) achieving optimal within-feature barrier coverage while balancing resistance parameters; (B) flake defectivity — the process is prone to flake defectivity due to inherent adhesive properties of nitride films. Several different parameters play a role in dictating the quality and quantity of the barrier film that is being deposited. This paper analyzes the impact of one such critical parameter — the AC bias during barrier deposition to modulate the chamfer coverage and the electrical Via-resistance. Furthermore it elucidates the methodology of addressing the source of massive killer flakes that cause severe pattern damage that act as \"killer\" defects for the dies. Post implementation of the changes discussed, the massive defects of interest that were sourced from the sputter process were completely eliminated. A detailed study supported by electrical and cross-sectional analysis allowed zeroing in on the optimal Bias power to derive the best possible chamfer stability while being able to achieve a lower Via-resistance as desired.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115435604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiple in/Multiple out, run to run controller for accurate and stable epitaxy processes: APC: Advanced process control","authors":"R. Benjamin, Lippl Gerhard, Lipp Stefan","doi":"10.1109/ASMC.2016.7491121","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491121","url":null,"abstract":"The development and usage of a Multiple in / Multiple out Run to Run Controller for complex epitaxy systems is the topic of this manuscript. The system uses dynamic status values and can be operated in two different modes. This allow to manufacture high accuracy epitaxial films.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Develop gap-fill process of shallow trench isolation in 450mm wafer by advanced Flowable CVD technology for sub-20nm node","authors":"Min-Hui Chen, Stock Chang","doi":"10.1109/ASMC.2016.7491115","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491115","url":null,"abstract":"In this study, a novel Flowable CVD process using non-carbon silicon based precursor has been developed for gap filling in 450mm wafer level, sub-20nm STI structure. To achieve 450mm wafer with aspect ratio 5:1 STI structure, guided DSA patterning and a-carbon hard-mask are applied. The various conditions have been screened in deposition, cure and anneal processes in order to result a void free and less Si damage performance. By SEM viewing and FT-IR analysis, the gap-fill profile and mechanism of film conversion are discussed.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"450mm PVD MHM TiN process development and process chamber evaluation using DC power system","authors":"Barry Wang, M. H. Chen, J. H. Xie, Stock Chang","doi":"10.1109/ASMC.2016.7491114","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491114","url":null,"abstract":"There are many excellent film properties of Titanium Nitride, such as high hardness, high corrosion resistance, good conductivity, low friction coefficient and a bright, golden color. In the past couple of years, it has been always used as barrier layer to inhibit diffusion of Al and Cu. In the most advance technology nodes, such as 20 nm, 16 nm and below, the metal hard mask (MHM) layer is necessary for better etching profile and less PR budget. Titanium Nitride has been used in BEOL (back-end of line) as MHM because of its film properties. In 450mm generation, cost saving and good productivity are the most important key factors. In this generation, we use DC power system as process chamber, and increase DC power to improve deposition rate. It will be a win-win approach to improve productivity and reduce cost. However, increasing DC power will transit stress in TiN to high compressive level. It will induce pattern wiggling. On the other hand, the U% of thickness is also considered at the same time. Faster deposition rate always induce worse U%. In order to get the best productivity and still have good stress and thickness U%, we study some solutions to develop 450mm PVD MHM TiN process and chamber evaluation by using DC power system.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132530174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. L. Manikonda, M. Medikonda, S. Patel, A. Bello, Jun Song, P. Mukundhan
{"title":"Copper process control with picosecond ultrasonic technology: A study","authors":"S. L. Manikonda, M. Medikonda, S. Patel, A. Bello, Jun Song, P. Mukundhan","doi":"10.1109/ASMC.2016.7491144","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491144","url":null,"abstract":"Copper topography control during the IC fabrication process is a critical process step as it maintains global planarity across the wafer. Die to die variations in Cu thickness occur during copper deposition and removal process at various metal levels. In this work, the challenges associated with obtaining good process control of Cu thickness using Metapulse tools is discussed. The stability and accuracy of the measurement recipe is analyzed and improved. It is seen that these improvements are directly correlated to reduced thickness variation thereby enabling tighter process control in advanced technologies.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131156606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Je-Boem Song, Jin-Tae Kim, Seung-Su Lee, Seong-Geun Oh, E. Oh, J. Yun
{"title":"Reliability assessment of anodic films under plasma etching process","authors":"Je-Boem Song, Jin-Tae Kim, Seung-Su Lee, Seong-Geun Oh, E. Oh, J. Yun","doi":"10.1109/ASMC.2016.7491133","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491133","url":null,"abstract":"Accelerated Degradation Test (ADT) is a test conducted under extreme stress conditions to accelerate degradation. In the plasma etching process, the life time of the anodic film deteriorates due to fatigue cracking, wear, and erosion arising from ion bombardment and radical reaction. However, ADT has yet to be studied in relation to plasma stress. A fault tree analysis are performed on plasma corrosion. The failure criterion of the corrosion is an increase in number of contamination particles. Since contamination particles are produced by an increase in by-products caused by corrosion, they can also be traced to the reduced mass of the oxide film. CF4, Ar, and O2 gas are used for the plasma corrosion test, and the acceleration factors are set as the pressure of the gases and the input power for plasma. This study proposes an efficient ADT design for the reliability analysis of anodic films under the plasma etching process.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}