M. Ndiaye, S. Dauzére-Pérés, C. Yugma, Lionel Rulliere, Gilles Lamiable
{"title":"Management of crisis situations in a large unified AMHS of a semiconductor manufacturing facility: IE: Industrial engineering","authors":"M. Ndiaye, S. Dauzére-Pérés, C. Yugma, Lionel Rulliere, Gilles Lamiable","doi":"10.1109/ASMC.2016.7491112","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491112","url":null,"abstract":"This paper deals with the management of operational crisis situations in a large unified Automated Material Handling System (AMHS) of a semiconductor wafer fabrication facility (fab). We propose an original approach to handle crisis situations, i.e. when a vehicle stops (due to a breakdown) on a rail and thus prevents other vehicles to use the same portion of the rail. This kind of crisis may lead to the blocking of many vehicles, thus impacting the fab productivity. To manage such situations, two Decision Support Systems (DSS) have been designed. The proposed DSS helped the fab to improve the reliability of lot deliveries.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132006995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. van den Heuvel, P. Foubert, B. Baudemprez, A. Lee, A. Cross, Kaushik Sah, Naoshin Haque, P. Parisi, O. Baris
{"title":"Process window discovery methodology development for advanced lithography","authors":"D. van den Heuvel, P. Foubert, B. Baudemprez, A. Lee, A. Cross, Kaushik Sah, Naoshin Haque, P. Parisi, O. Baris","doi":"10.1109/ASMC.2016.7491105","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491105","url":null,"abstract":"With the continued need for shrinking patterning dimensions in semiconductor manufacturing, new lithography techniques, such as advanced multi-patterning, are being introduced into production for 10nm node and beyond, and others, such as EUV, are nearing production requirements. Previous work [1] has shown that these new developments introduce new challenges in terms of qualifying the process window. In the past the boundaries of the overlapping process window (focus and exposure latitude in which all structures in a given layout print within the specifications) were mainly defined by design and OPC related systematic defects and lithographers and defect engineers were relying on Process Window Qualification (PWQ) methods to discover these systematic defects. In more advanced nodes however, the process window is also impacted by FAB related sources (wafer non-uniformity, process variations) or, in case of multi-patterning schemes, also by interactions between the different masks. To take these factors into account PWQ has now evolved into a new methodology called Process Window Discovery (PWD). This paper will focus on further development of this methodology. We will further focus on techniques to enhance the sensitivity of the broadband plasma defect inspection and we will demonstrate how this metrology can highlight intra-field and across-wafer variations. The final step of this work will be to implement this methodology to compare the overlapping process windows of two identical metal layers with 2D logic patterns, of which one layer will be patterned with EUV single patterning and the other will be patterned with 193i triple litho-etch patterning (LE3). For 193i LE3 a special focus goes on the detection of overlay critical hotspots and defining the overlay variation related process window. For EUV special attention goes to EUV specific hotspots and typical sources of variations across wafer.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":" 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120829947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Subramaniyan, Domingo Ferrer Luppi, N. Makela, L. Bauer, A. Madan, R. Murphy, F. Baumann, Kriti Kohli, C. Parks
{"title":"Investigation on critical thickness dependence of ALD TiN diffusion barrier in MOL","authors":"A. Subramaniyan, Domingo Ferrer Luppi, N. Makela, L. Bauer, A. Madan, R. Murphy, F. Baumann, Kriti Kohli, C. Parks","doi":"10.1109/ASMC.2016.7491156","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491156","url":null,"abstract":"Titanium nitride (TiN), a refractory material is actively been used as a diffusion barrier in Middle-of-the-Line (MOL) contacts. In the typical MOL stack (titanium (Ti)/TiN/tungsten(W)), it acts as a fluorine (F) diffusion barrier and also as an adhesion layer to W. During W deposition, F from W precursor chemistry can react with Ti to form a highly resistive titanium fluoride (TiFx) compound. The formation of TiFx creates >200% volume expansion which can result in cracks on the TiN layer or W delamination. In order to be an effective diffusion barrier layer, TiN has to be dense which demands a critical thickness. In this work, we study the materials properties of ALD TiN as a function of thickness in the range 11-35 Â. We found a linear increase in resistivity of TiN on Ti with thickness. Columnar structured microstructure was observed for TiN films with thickness 30.4 and 34.7 Â. These films were also found to be slightly denser. TEM electron diffraction indicated that the 34.7 Â film is preferentially oriented along [111]. The roughness of the film increases with thickness. Three roughness zones with different crystallization modes have been identified which indicates thickness dependent crystallization. From our study, it is clear that in addition to density, the formation of preferential orientation of TiN might play a role for critical thickness requirement.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123967257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quality control for ultrafiltration of ultrapure water production for high end semiconductor manufacturing","authors":"J. Ruth, R. Berndt","doi":"10.1109/ASMC.2016.7491077","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491077","url":null,"abstract":"Ultrafiltration is applied to remove particles, colloids and large macromolecules from ultrapure water for semiconductor device manufacturing. Early detection of leaks, pinholes and fiber breaks in membrane modules is an essential prerequisite for this ultimate task and a first step for defect free manufacturing. Particle monitoring alone is not sufficient. Periodic pressure-hold testing enables much higher sensitivity and is an indispensable complementary measure for preventive maintenance.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129541338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Detection and classification of gate to S/D shorts using charge dynamics","authors":"M. Lei, Kevin Wu, Qing Tian, Yan Zhao","doi":"10.1109/ASMC.2016.7491153","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491153","url":null,"abstract":"Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) which stems from the transistor level response from electron beam inspection (EBI) scan. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for true short defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results for various shorting mechanisms.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131033071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Bhat, A. Chadwick, Hong Wei, Ankur Sharma, Sivakumar Kumarasamy, M. Stoker, S. Hildreth, K. Chung, Ying Hao Hsieh
{"title":"Parameters influencing unwanted growth during epitaxial growth of SiGe","authors":"T. Bhat, A. Chadwick, Hong Wei, Ankur Sharma, Sivakumar Kumarasamy, M. Stoker, S. Hildreth, K. Chung, Ying Hao Hsieh","doi":"10.1109/ASMC.2016.7491128","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491128","url":null,"abstract":"In the advanced nodes of 28nm and below, small defects too can have a significant impact on the final yield results of wafers. As the technology node advances it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. In this paper we evaluate the influence of various processing parameters on the extent of \"Unwanted Growth\" defects on wafers in the form of small SiGe nodules (20–50nm) left over post selective SiGe epitaxial growth for strained CMOS Si. These defects, depending on where they grow/land, can lead to failure of the chip. An optimization of the processing parameters to minimize the occurrence of these defects leads to yield gain and cost savings for High Volume Manufacturing (HVM).","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126442623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Niu, M. Raymond, V. Kamineni, J. Fronheiser, S. Siddiqui, H. Niimi, J. Dechene, A. Labonté, P. Adusumilli, A. Carr, J. Shearer, J. Demarest, L. Jiang, J. Li, R. Hengstebeck
{"title":"Interface preservation during Ge-rich source/drain contact formation","authors":"C. Niu, M. Raymond, V. Kamineni, J. Fronheiser, S. Siddiqui, H. Niimi, J. Dechene, A. Labonté, P. Adusumilli, A. Carr, J. Shearer, J. Demarest, L. Jiang, J. Li, R. Hengstebeck","doi":"10.1109/ASMC.2016.7491158","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491158","url":null,"abstract":"Contact engineering of Ge-rich source/drain is of critical importance for the development of advanced nano-scale CMOS technology nodes. Germanosilicide or Germanide contacts with low Schottky barrier height are highly desirable to achieve low contact resistance for a Ge-rich source/drain. However, practical integration of Ge-rich SiGe into devices is complicated by its unique physical and chemical properties as compared to Si-rich epitaxial SiGe. We have observed significant erosion along the SiGe interface with its dielectric cap layer. The N2-H2 remote plasma resist strip process has been shown to trigger this erosion when GeO2 exists together with SiO2 at the interface. The integrity of Ge-rich SiGe contact interface can be preserved by replacing the N2-H2 remote plasma resist strip with an O2-based photoresist ash process. Cross-sectional STEM and EDX elemental analysis have confirmed Germanide and Germanosilicide formation at the Ge-rich SiGe contact interface.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. W. Ma, C. Lai, Zhi Min Zhang, W. Huang, Chao Yong Li, C. S. Zhou, Chee Kong Leong
{"title":"Optimized circuit design and novel Al deposition process cure power short failure caused by Al whisker","authors":"Y. W. Ma, C. Lai, Zhi Min Zhang, W. Huang, Chao Yong Li, C. S. Zhou, Chee Kong Leong","doi":"10.1109/ASMC.2016.7491162","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491162","url":null,"abstract":"Power short (PS) bin failure due to Al bridging in bond pad regions originated from Al whisker, caused severe yield loss in advanced technology nodes. A comprehensive study on circuit design impact on Al whisker bridging issue was carried out and it was found that increasing Al metal spacing reduced Al whisker bridging. Furthermore, through optimization of process, the novel Al high power deposition recipe demonstrated that power short failure caused by Al whisker could be completely eliminated. The two proposed solutions provide a guideline to solve Al whisker for more advanced technology nodes.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116686707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transient leakage of point-defects in gate oxide due to spatially transported constant-source of phosphorus contaminants","authors":"L. Sheng, B. Williams, T. Haskett, E. Glines","doi":"10.1109/ASMC.2016.7491164","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491164","url":null,"abstract":"The transient leakage specifically within pMOS gate oxide has been for the first time connected to excessive phosphorus contaminants as a constant source of defects at gate oxidation. A 3D spatial analysis of defect transportation and formation was critical to the first-time success in design of experiment. By avoiding a significant build-up of phosphorus-contaminants inside the gate oxidation furnace, the pMOS-specific gate oxide defects due to the transient leakage have been eliminated, thus improving product yield and potentially enhancing gate oxide reliability.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129400578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Ferrer, A. Lévesque, Asli Sirman, Junedong Lee, A. Subramaniyan, L. Lanzerotti, D. Hilscher, E. Alptekin
{"title":"Precleans challenges on middle-of-the-line contacts for 14nm technologies and beyond","authors":"D. Ferrer, A. Lévesque, Asli Sirman, Junedong Lee, A. Subramaniyan, L. Lanzerotti, D. Hilscher, E. Alptekin","doi":"10.1109/ASMC.2016.7491167","DOIUrl":"https://doi.org/10.1109/ASMC.2016.7491167","url":null,"abstract":"In-situ dry cleans of silicon-based surfaces preceding the metallization process step have a crucial impact on contact resistance, yield and reliability of middle-of-the-line (MOL) local interconnects. Existing precleaning techniques meet numerous challenges predominantly originated from reduced device geometries such as critical dimensions enlargements, epitaxial junctions gouging and insufficient native oxide removal. Reactive chemical cleans employing remote plasma assisted with NF3/NH3 gas mixtures designated as SiCoNi™ include complex etchant-surface interactions. This report discusses junction-to-metal interfacial aspects of physical and chemical precleans applied to MOL contacts. The fundamental mechanisms that govern clean efficiency of MOL contacts are analyzed in order to insure the manufacturability of defect-free local interconnects.","PeriodicalId":264050,"journal":{"name":"2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131595364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}