通过优化TaN势垒PVD工艺改善28nm 90p铜线互连中的超模式杀手缺陷和增强特征内屏障覆盖

B. Rajagopalan, J. Laloe, M. Silvestre, E. Ramanathan, Sohana Khanal, Alain Laval, Q. Ge, N. Takahashi, A. S. Mahalingam, S. L. Liew, Robert Teagle
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引用次数: 1

摘要

BEOL屏障种子沉积工艺是实现理想的电气和电迁移性能的关键组成部分,同时平衡步长覆盖范围。该工艺对晶圆良率参数也有多重影响,因为它服务于不同金属水平的多个通道。障碍溅射沉积的两个主要挑战是:(A)在平衡电阻参数的同时实现最佳的特征内障碍覆盖;(B)片状缺陷-由于氮化膜固有的粘合性能,该工艺容易出现片状缺陷。有几个不同的参数决定了所沉积的屏障膜的质量和数量。本文分析了阻挡层沉积过程中交流偏压这一关键参数对倒角覆盖和过孔电阻的影响。此外,它阐明了解决大量杀手片的来源的方法,造成严重的图案损坏,作为模具的“杀手”缺陷。在实施了所讨论的变更后,源自溅射过程的大量缺陷被完全消除了。在电气和截面分析的支持下,详细的研究允许对最佳偏置功率进行归零,以获得最佳的倒角稳定性,同时能够实现所需的更低的过通电阻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Extra-pattern killer defectivity improvement and enhancement of within-feature barrier coverage by optimization of TaN barrier PVD process in 90p Cu wire interconnects for 28nm technology
The BEOL Barrier-Seed deposition process is a key component in achieving the desired electrical and electro-migration performance while balancing the step coverage. The process also has a multifold impact on wafer yield parametric since it serves multiple passes for the various metal levels. Two major challenges with the barrier sputter deposition are: (A) achieving optimal within-feature barrier coverage while balancing resistance parameters; (B) flake defectivity — the process is prone to flake defectivity due to inherent adhesive properties of nitride films. Several different parameters play a role in dictating the quality and quantity of the barrier film that is being deposited. This paper analyzes the impact of one such critical parameter — the AC bias during barrier deposition to modulate the chamfer coverage and the electrical Via-resistance. Furthermore it elucidates the methodology of addressing the source of massive killer flakes that cause severe pattern damage that act as "killer" defects for the dies. Post implementation of the changes discussed, the massive defects of interest that were sourced from the sputter process were completely eliminated. A detailed study supported by electrical and cross-sectional analysis allowed zeroing in on the optimal Bias power to derive the best possible chamfer stability while being able to achieve a lower Via-resistance as desired.
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