{"title":"Energy-efficient mobile data transport via online multi-network packet scheduling","authors":"Aaron Cote, A. Meyerson, Brian Tagiku","doi":"10.1109/GREENCOMP.2010.5598312","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598312","url":null,"abstract":"We explore a novel online packet scheduling model related to energy-efficiency in mobile data transport. This model incorporates multiple networks with non-persistent connectivities where we only know which networks are available in the current timestep. When a packet arrives, it specifies a deadline and, for each network, a value it is worth if sent over that network. Our goal is to maximize the total value of packets we send by their deadlines. To encourage energy-efficiency, our model requires that packets have larger values for more energy-efficient networks. We demonstrate low-constant-competitive algorithms for this problem and several restrictions. We also provide lower bounds which closely match our competitive ratios and, under some restrictions, are tight.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126849306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance evaluation of different encryption schemes on portable and mobile platforms","authors":"Fadi Almasalha, R. Hasimoto-Beltrán, A. Khokhar","doi":"10.1109/GREENCOMP.2010.5598284","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598284","url":null,"abstract":"Encryption is becoming an increasingly dominant component in online and mobile applications. While robust security is an important property desired in encryption schemes, it is equally important for such schemes to be highly energy efficient. In this paper we evaluate traditional AES implementations and non-traditional Chaotic Maps based encryption schemes. Our experiments reveal that Chaotic Maps based schemes outperform the traditional AES implementation in terms of CPU usage, encryption speed, and energy consumption. Particularly they consume 300–400 % less CPU, and have over 250% faster encryption speed. In addition, the energy usage of the Chaotic scheme for a given input rate or size is 3 times better compared to the other systems considered. However, the performance also depends on the floating point capability of the platform; a suitable scheme may be chosen depending on the battery and CPU power of platform. The performance results reported in this paper are based on experiments on desktops, laptops, netbooks, and PDAs.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123205037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kurowski, Ariel Oleksiak, Michael L. Witkowski, J. Nabrzyski
{"title":"Distributed power management and control system for sustainable computing environments","authors":"K. Kurowski, Ariel Oleksiak, Michael L. Witkowski, J. Nabrzyski","doi":"10.1109/GREENCOMP.2010.5598291","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598291","url":null,"abstract":"As the notion of Green Computing becomes more popular in the IT world, new power saving features start to appear in both computer hardware and software. The difficulty of leveraging existing means of power management and control increases with the scale of operations, making a networked approach to the problem a necessity. In this paper we present the SMOA Devices architecture, a distributed solution for monitoring and management of power consumption in computer systems. We discuss its features and characteristics, and explain what makes it suitable for a broad range of power saving and management applications.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116567126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power SRAM cell design for FinFET and CNTFET technologies","authors":"J. Delgado-Frías, Zhe Zhang, M. A. Turi","doi":"10.1109/GREENCOMP.2010.5598266","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598266","url":null,"abstract":"Implementations of SRAM cells in FinFET and carbon nanotube FET (CNTFET) technologies are presented in this paper. The International Technology Roadmap for Semiconductors has identified these technologies as likely candidates to replace bulk CMOS. Leakage current is one of the major contributors in the power consumption in SRAM arrays; FinFETs have been shown to greatly reduce leakage current. The FinFET memory cells are presented. These cells dissipate 0.49 µW of static power. The CNTFET memory requires 0.195 µW of static power. In current synthesis processes Metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. This CNTFET memory with metallic tolerance dissipates 0.21 µW of static power.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134132283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hitoshi Nagasaka, N. Maruyama, Akira Nukada, Toshio Endo, S. Matsuoka
{"title":"Statistical power modeling of GPU kernels using performance counters","authors":"Hitoshi Nagasaka, N. Maruyama, Akira Nukada, Toshio Endo, S. Matsuoka","doi":"10.1109/GREENCOMP.2010.5598315","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598315","url":null,"abstract":"We present a statistical approach for estimating power consumption of GPU kernels. We use the GPU performance counters that are exposed for CUDA applications, and train a linear regression model where performance counters are used as independent variables and power consumption is the dependent variable. For model training and evaluation, we use publicly available CUDA applications, consisting of 49 kernels in the CUDA SDK and the Rodinia benchmark suite. Our regression model achieves highly accurate estimates for many of the tested kernels, where the average error ratio is 4.7%. However, we also find that it fails to yield accurate estimates for kernels with texture reads because of the lack of performance counters for monitoring texture accesses, resulting in significant underestimation for such kernels.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127874048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Narasimhan, D. R. McIntyre, F. Wolff, Yu Zhou, D. Weyer, S. Bhunia
{"title":"A supply-demand model based scalable energy management system for improved energy utilization efficiency","authors":"S. Narasimhan, D. R. McIntyre, F. Wolff, Yu Zhou, D. Weyer, S. Bhunia","doi":"10.1109/GREENCOMP.2010.5598260","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598260","url":null,"abstract":"Harvesting energy from the environment can play an important role in reducing the dependency of an electronic system to primary energy sources (i.e. AC power or battery). For reliable and efficient energy harvesting while assuring best user experience, it is important to manage, route and match the harvested energy with the demand of various energy sources. In the most general case, multiple different energy sources can be used to provide energy to multiple different energy users. In this work, we propose a scalable rule-based energy management system for managing the acquisition, mixing, delivery and storage of energy for arbitrary collection of energy sources and users, which are characterized with different energy generation and consumption parameters. The system uses economics inspired supply-demand model for efficiently managing energy distribution between a set of energy sources and users. The energy allocation procedure tries to maximize the energy utilization efficiency of the sources while satisfying the demand of the users in order of their associated priorities, without starving an already allocated user. Simulation results for example scenarios show the effectiveness of the proposed approach for improving the energy utilization and lifetime of the energy sources.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115497648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy aware scheduling for DAG structured applications on heterogeneous and DVS enabled processors","authors":"Venkateswaran Shekar, B. Izadi","doi":"10.1109/GREENCOMP.2010.5598275","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598275","url":null,"abstract":"The trend towards ever more powerful and faster processors has led to an enormous increase in power consumption. This paper focuses on scheduling tasks in a heterogeneous environment with DVS enabled processors to minimize both execution time and energy consumed. The proposed algorithm, called Energy-Dynamic Level Scheduling (EDLS), favors low-energy consuming processors by introducing a cost factor that affects scheduling decisions. Our scheme allows for trade offs between energy consumption and the desired performance. Our simulation results exhibit significant power savings at a reasonable increase in overall execution time. Moreover, our results demonstrates a high degree of correlation between the energy saving and the increase in the heterogeneity of processors.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114851300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy-efficient processing through adaptation and resiliency","authors":"J. Tschanz","doi":"10.1109/GREENCOMP.2010.5598270","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598270","url":null,"abstract":"Today's SoC devices are often constrained by both performance and power requirements. New software capabilities and usage models demand more processing power than ever before, however the increased integration requires advanced power management techniques. Process scaling, which makes this all possible, also leads to increased susceptibility to variations - static process variations as well as dynamic environmental variations in voltage, temperature, and transistor aging.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126145386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Investigation on the power efficiency of multi-core and GPU Processing Element in large scale SIMD computation with CUDA","authors":"D. Ren, R. Suda","doi":"10.1109/GREENCOMP.2010.5598300","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598300","url":null,"abstract":"CPU-GPU Processing Element (PE) has become a very popular architecture to construct modern multiprocessing system because of its high performance on massively parallel processing and vector computations. Power dissipation is one of the important factors influencing design development of High Performance Computing (HPC) as a large scale scientific computation may use thousands of processors and hundreds hours of continuous execution that will result enormous energy predicament. Enhancing the utilizations of an individual PE to reach its best computation capability and power efficiency is valuable for saving the overall power cost of large multi-processing systems. Power performance of a CUDA PE is dependent on electrical features of the inside hardware components and their interconnections; also high level applications and the parallel algorithms performed on it. Based on measurements and experimental evaluations, in this work we provide a load sharing method to adjust the workload assignment within the CPU and GPU components inside a CUDA PE in order to optimize the overall power efficiency. The improvement on computation time and power consumption has been validated by examining the program executions when above method is applied on real systems.","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129709702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bhavishya Goel, S. Mckee, R. Gioiosa, Karan Singh, M. Bhadauria, M. Cesati
{"title":"Portable, scalable, per-core power estimation for intelligent resource management","authors":"Bhavishya Goel, S. Mckee, R. Gioiosa, Karan Singh, M. Bhadauria, M. Cesati","doi":"10.1109/GREENCOMP.2010.5598313","DOIUrl":"https://doi.org/10.1109/GREENCOMP.2010.5598313","url":null,"abstract":"Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging. Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application-independent models for four different (four- to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1%–5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%–4.4% overall).","PeriodicalId":262148,"journal":{"name":"International Conference on Green Computing","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115963603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}