Low power SRAM cell design for FinFET and CNTFET technologies

Implementations of SRAM cells in FinFET and carbon nanotube FET (CNTFET) technologies are presented in this paper. The International Technology Roadmap for Semiconductors has identified these technologies as likely candidates to replace bulk CMOS. Leakage current is one of the major contributors in the power consumption in SRAM arrays; FinFETs have been shown to greatly reduce leakage current. The FinFET memory cells are presented. These cells dissipate 0.49 µW of static power. The CNTFET memory requires 0.195 µW of static power. In current synthesis processes Metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. This CNTFET memory with metallic tolerance dissipates 0.21 µW of static power.