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2011 3rd IEEE International Memory Workshop (IMW)最新文献

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The Non-Volatile Memory Industry - A Personal Journey 非易失性存储器产业-个人旅程
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-05-22 DOI: 10.1109/IMW.2011.5873193
E. Harari
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引用次数: 4
Doping Engineering for Random Telegraph Noise Suppression in Deca-Nanometer Flash Memories 十纳米快闪存储器中随机电报噪声抑制的掺杂工程
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-05-22 DOI: 10.1109/IMW.2011.5873216
A. Ghetti, S. Amoroso, A. Mauri, C. M. Compagnoni
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引用次数: 6
An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies 一种用于20nm以下NAND闪存技术的超薄混合浮栅概念
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-05-22 DOI: 10.1109/IMW.2011.5873198
D. Wellekens, P. Blomme, M. Rosmeulen, T. Schram, A. Cacciato, I. Debusschere, J. van Houdt, S. Van Aerde
{"title":"An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies","authors":"D. Wellekens, P. Blomme, M. Rosmeulen, T. Schram, A. Cacciato, I. Debusschere, J. van Houdt, S. Van Aerde","doi":"10.1109/IMW.2011.5873198","DOIUrl":"https://doi.org/10.1109/IMW.2011.5873198","url":null,"abstract":"A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.","PeriodicalId":261995,"journal":{"name":"2011 3rd IEEE International Memory Workshop (IMW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications 用于高性能和低功耗微控制器应用的高度优化的基于纳米晶体的分闸闪存
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-05-22 DOI: 10.1109/IMW.2011.5873213
J. Yater, C. Hong, S. Kang, D. Kolar, B. Min, J. Shen, G. Chindalore, K. Loiko, B. Winstead, S. Williams, H. Gasquet, M. Suhail, K. Broeker, E. Lepore, A. Hardell, W. Malloch, R. Syzdek, Y. Chen, Y. Ju, S. Kumarasamy, H. Liu, L. Lei, B. Indajang
{"title":"Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications","authors":"J. Yater, C. Hong, S. Kang, D. Kolar, B. Min, J. Shen, G. Chindalore, K. Loiko, B. Winstead, S. Williams, H. Gasquet, M. Suhail, K. Broeker, E. Lepore, A. Hardell, W. Malloch, R. Syzdek, Y. Chen, Y. Ju, S. Kumarasamy, H. Liu, L. Lei, B. Indajang","doi":"10.1109/IMW.2011.5873213","DOIUrl":"https://doi.org/10.1109/IMW.2011.5873213","url":null,"abstract":"NA","PeriodicalId":261995,"journal":{"name":"2011 3rd IEEE International Memory Workshop (IMW)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127651206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The Effect of Tunnel Barrier at Resistive Switching Device for Low Power Memory Applications 隧道势垒对低功耗存储器中电阻开关器件的影响
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-05-22 DOI: 10.1109/IMW.2011.5873243
Hyejung Choi, J. Yi, Sangmin Hwang, Sangkeum Lee, Seokpyo Song, Seunghwan Lee, Jaeyeon Lee, Donghee Son, Jinwon Park, Suk-Ju Kim, Ja-Yong Kim, Sunghoon Lee, Jiwon Moon, Choidong Kim, Jungwoo Park, M. Joo, J. Roh, Sungki Park, Sungwoong Chung, Ju-Hee Rhee, Sung-Joo Hong
{"title":"The Effect of Tunnel Barrier at Resistive Switching Device for Low Power Memory Applications","authors":"Hyejung Choi, J. Yi, Sangmin Hwang, Sangkeum Lee, Seokpyo Song, Seunghwan Lee, Jaeyeon Lee, Donghee Son, Jinwon Park, Suk-Ju Kim, Ja-Yong Kim, Sunghoon Lee, Jiwon Moon, Choidong Kim, Jungwoo Park, M. Joo, J. Roh, Sungki Park, Sungwoong Chung, Ju-Hee Rhee, Sung-Joo Hong","doi":"10.1109/IMW.2011.5873243","DOIUrl":"https://doi.org/10.1109/IMW.2011.5873243","url":null,"abstract":"NA","PeriodicalId":261995,"journal":{"name":"2011 3rd IEEE International Memory Workshop (IMW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126332589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Process Technologies Enabling Future Memory Platforms 实现未来存储平台的工艺技术
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-05-22 DOI: 10.1109/IMW.2011.5873195
Gillian Lee, Po-Ta Chen, Sung-Woo Kim
{"title":"Process Technologies Enabling Future Memory Platforms","authors":"Gillian Lee, Po-Ta Chen, Sung-Woo Kim","doi":"10.1109/IMW.2011.5873195","DOIUrl":"https://doi.org/10.1109/IMW.2011.5873195","url":null,"abstract":"NA","PeriodicalId":261995,"journal":{"name":"2011 3rd IEEE International Memory Workshop (IMW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116796878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application 基于垂直硅纳米线的无结可堆叠SONOS存储器的三维应用
2011 3rd IEEE International Memory Workshop (IMW) Pub Date : 2011-04-25 DOI: 10.1109/VTSA.2011.5872271
Y. Sun, H. Y. Yu, N. Singh, E. Gnani, G. Baccarani, K. Leong, G. Lo, D. Kwong
{"title":"Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application","authors":"Y. Sun, H. Y. Yu, N. Singh, E. Gnani, G. Baccarani, K. Leong, G. Lo, D. Kwong","doi":"10.1109/VTSA.2011.5872271","DOIUrl":"https://doi.org/10.1109/VTSA.2011.5872271","url":null,"abstract":"NA","PeriodicalId":261995,"journal":{"name":"2011 3rd IEEE International Memory Workshop (IMW)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116756004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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