An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies

Abstract

A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.