Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003最新文献_第4页

Comparison of branching CORDIC implementations 分支CORDIC实现的比较

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212845

Abhishek Singh, D. Phatak, T. Goff, Mike Riggs, J. Plusquellic, C. Patel

引用次数: 2

Energy aware register file implementation through instruction predecode 能量感知寄存器文件的实现，通过指令的前身

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212832

J. Ayala, M. López-Vallejo, A. Veidenbaum, Carlos A. Lopez

引用次数: 21

A floating-point CORDIC based SVD processor 基于浮点CORDIC的SVD处理器

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212843

Zhaohui Liu, K. Dickson, J. McCanny

引用次数: 15

A family of parallel-prefix modulo 2/sup n/-1 adders 一组并行前缀模2/sup n/-1加法器

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212856

G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, C. Efstathiou

引用次数: 12

Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures 在粗粒度可重构体系结构上评估媒体应用程序的内存体系结构

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212841

Jongeun Lee, Kiyoung Choi, N. Dutt

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引用次数: 15

Application-specific computing with adaptive register file architectures 具有自适应寄存器文件架构的特定于应用程序的计算

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212842

R. Sangireddy, Arun Kumar Somani

{"title":"Application-specific computing with adaptive register file architectures","authors":"R. Sangireddy, Arun Kumar Somani","doi":"10.1109/ASAP.2003.1212842","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212842","url":null,"abstract":"The demand for higher computing power to effectively execute compute-intensive functions and thus more on-chip computing resources is ever increasing. On the other hand, applications that demand larger on-chip memory bandwidth are continuously emerging. We propose adaptive register file computing (ARC) unit, a novel on-chip processing element that leverages application-specific processing capabilities. The ARC unit supplements a conventional register file to provide large memory bandwidth, or acts as a configurable computing unit to provide higher on-chip computing capacity, depending on the requirement of a specific application. When an out-of-order 8-wide issue superscalar processor is supplemented with the ARC unit to process matrix multiplication, a compute-intensive core function in most multimedia applications, results show a performance increase of up to 12%. Similarly, a 9% performance enhancement is seen when the matrix multiplication is performed in an out-of-order 4-wide issue superscalar processor supplemented with the ARC unit. We also discuss the microarchitecture level details for the implementation of the ARC unit.","PeriodicalId":261592,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123154804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Context-aware process networks 情境感知流程网络

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212825

H. W. V. Dijk, H. Sips, E. Deprettere

引用次数: 24

A VLSI architecture for advanced video coding motion estimation 一种用于高级视频编码运动估计的VLSI架构

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212853

S. Y. Yap, J. McCanny

引用次数: 39

Switched memory architectures - moving beyond systolic arrays 切换内存架构——超越收缩数组

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212827

Lakshminarayanan Renganarayanan, S. Rajopadhye

引用次数: 2

Using group theory to specify application specific interconnection networks for SIMD DSPs 使用群理论为SIMD dsp指定特定应用的互连网络

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212829

Thorsten Dräger, G. Fettweis

引用次数: 4