Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003最新文献

Unified radix-4 multiplier for GF(p) and GF(2^n) GF(p)和GF(2^n)的统一基数-4乘子

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-26 DOI: 10.1109/ASAP.2003.1212846

Lai-Sze Au, N. Burgess

引用次数: 11

Modular multiplication for FPGA implementation of the IDEA block cipher 模块化乘法用FPGA实现的IDEA分组密码

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212864

Jean-Luc Beuchat

引用次数: 23

Multi-dimensional incremental loop fusion for data locality 数据局部性的多维增量环路融合

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212826

Sven Verdoolaege, M. Bruynooghe, Gerda Janssens, F. Catthoor

引用次数: 69

Reconfigurable Viterbi decoding using a new ACS pipelining technique 使用新的ACS流水线技术的可重构维特比解码

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212859

Yiqun Zhu, M. Benaissa

引用次数: 13

Concurrent fault detection in a hardware implementation of the RC5 encryption algorithm 并发故障检测在硬件上实现了RC5加密算法

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212865

G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, V. Piuri

{"title":"Concurrent fault detection in a hardware implementation of the RC5 encryption algorithm","authors":"G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, V. Piuri","doi":"10.1109/ASAP.2003.1212865","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212865","url":null,"abstract":"Recent research has shown that fault diagnosis and possibly fault tolerance are important features when implementing cryptographic algorithms by means of hardware devices. In fact, some security attack procedures are based on the injection of faults. At the same time, hardware implementations of cryptographic algorithms, i.e. crypto-processors, are becoming widespread. There is however, only very limited research on implementing fault diagnosis and tolerance in crypto-algorithms. Fault diagnosis is studied for the RC5 crypto-algorithm, a recently proposed block-cipher algorithm that is suited for both software and hardware implementations. RC5 is based on a mix of arithmetic and logic operations, and is therefore a challenge for fault diagnosis. We study fault propagation in RC5, and propose and evaluate the cost/performance tradeoffs of several error detecting codes for RC5. Costs are estimated in terms of hardware overhead, and performances in terms of fault coverage. Our most important conclusion is that, despite its nonuniform nature, RC5 can be efficiently protected by using low-cost error detecting codes.","PeriodicalId":261592,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An efficient disk-array-based server design for a multicast video streaming system 一种高效的基于磁盘阵列的多播视频流服务器设计

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212851

P. Chan, Jack Y. B. Lee

{"title":"An efficient disk-array-based server design for a multicast video streaming system","authors":"P. Chan, Jack Y. B. Lee","doi":"10.1109/ASAP.2003.1212851","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212851","url":null,"abstract":"Recently, a number of researchers have started to investigate new video-on-demand (VoD) architectures using batching, patching and periodic broadcasting. These architectures, compared to traditional unicast VoD systems, are much more scalable and can serve thousands or even millions of clients concurrently. Nevertheless, existing studies are usually focused on architectural issues. The problem of designing an efficient server to implement these new multicast VoD architectures has received little attention. While existing server designs using round-based schedulers can still be used, results show that such designs are suboptimal as they do not exploit the characteristics of fixed-schedule periodic broadcasting channels. We address this challenge by presenting an efficient server design for a recent multicast VoD architecture called Super-Scalar Video-on-Demand (SS-VoD). Results show that the efficient server design can increase the system capacity by 60% compared to traditional video server designs. We present details of this new server design, derives a performance model, and analyzes it using numerical results.","PeriodicalId":261592,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117207249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nanotechnology in the development of future computing systems 纳米技术在未来计算机系统发展中的作用

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212835

Toshishige Yamada, M. Meyyappan

引用次数: 1

Variable-length instruction compression for area minimization 面积最小化的变长指令压缩

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212839

Piia Simonen, I. Saastamoinen, J. Nurmi

引用次数: 2

Circuit characteristics of molecular electronic components 分子电子元件的电路特性

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212836

D. Janes, Subhasis Ghosh, Jaewon Choi, S. Lodha

{"title":"Circuit characteristics of molecular electronic components","authors":"D. Janes, Subhasis Ghosh, Jaewon Choi, S. Lodha","doi":"10.1109/ASAP.2003.1212836","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212836","url":null,"abstract":"Electronic devices based on single molecules, or small assemblies of molecules, are attracting much attention as intrinsically nanoscale devices that can add functionality such as optical emission and nonvolatile storage to silicon-based electronics. One of the key issues in these devices is the nature of the microscopic contacts to the active molecules and the need to develop well-controlled interfaces in order to achieve low-resistance contacts. We describe the formation of suitable contact structures in the form of nanometer scale \"break junctions\" in gold lines, formed by lithographic or electrical means. The structure provides a lead frame for realizing high-quality contacts to nanometer-size molecules and nanoparticles with selective docking achieved by end-groups such as thiol (-SH). Metal-molecule-metal junctions can be formed by chemisorbing short molecules such as 1,4-benzenedithiol on the two electrodes. Current-voltage (I-V) characteristics have been measured for configurations including small numbers of molecules directly bonded in the junction and molecule/nanocluster/molecule assemblies. These junctions are being used as test beds to study electrical conduction through different types of engineered-molecules, and to subsequently develop circuit level models. By integrating these molecules with electrical contacts, selective microscopic events (e.g. doping events or gas docking) can be coupled to external circuitry.","PeriodicalId":261592,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125611421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Systematic register bypass customization for application-specific processors 针对特定应用程序处理器的系统寄存器旁路定制

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI: 10.1109/ASAP.2003.1212830

Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, M. Smelyanskiy, S. Mahlke

{"title":"Systematic register bypass customization for application-specific processors","authors":"Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, M. Smelyanskiy, S. Mahlke","doi":"10.1109/ASAP.2003.1212830","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212830","url":null,"abstract":"Register bypass provides additional datapaths to eliminate data hazards in processor pipelines. The difficulty with register bypass is that the cost of the bypass network is substantial and grows substantially as processor width or pipeline depth are increased. For a single application, many of the bypass paths have extremely low utilization. Thus, there is an important opportunity in the design of application-specific processors to remove a large fraction of the bypass cost while maintaining performance comparable to a processor with full bypass. We propose a systematic design customization process along with a bypass-cognizant compiler scheduler. For the former, we employ iterative design space exploration wherein successive processor designs are selected based on bypass utilization statistics combined with the availability of redundant bypass paths. Compiler scheduling for sparse bypass processors is accomplished by prioritizing function unit choices for each operation prior to scheduling using global information. Results show that for a 5-issue customized VLIW processor, 70% of the bypass cost is eliminated while sacrificing only 10% performance.","PeriodicalId":261592,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30