Variable-length instruction compression for area minimization

Abstract

Memories comprise a significant part of chips in embedded applications, thus also contributing considerably to the costs. We present a variable-length compression scheme for reducing program memory footprint in a 32-bit DSP processor. The compression method is based on a static program code analysis. Short operand fields do not provide sufficient repetition individually, so the compression is realized by handling all operands of an instruction as one field. The more a certain operand combination is used, the shorter it is coded. The original combination is placed on a look-up table and the coded bit pattern forms an index to that table. The compression results that are achieved in two test applications are 46% (audio decoder) and 51% (video decoder).