一组并行前缀模2/sup n/-1加法器

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 Pub Date : 2003-06-24 DOI:10.1109/ASAP.2003.1212856

G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, C. Efstathiou

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引用次数: 12

摘要

我们揭示了模2/sup n/-1加法的幂等性的循环性质。然后基于这一性质，我们为每个n导出一个最小逻辑深度模数为2/sup n/-1的加法器，它允许在运算符数量、内部线长度和内部节点的扇出之间进行若干权衡。使用静态CMOS实现收集的性能数据显示，所提出的架构在面积和/或运行速度方面优于所有先前报道的架构。

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A family of parallel-prefix modulo 2/sup n/-1 adders

We reveal the cyclic nature of idempotency in the case of modulo 2/sup n/-1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2/sup n/-1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.

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来源期刊

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003

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