2011 IEEE International Test Conference最新文献_第4页

A fully cell-based design for timing measurement of memory 一个完全基于单元格的存储器定时测量设计

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139150

Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao

引用次数: 7

Lithography aware critical area estimation and yield analysis 了解光刻关键区域估计和良率分析

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139152

P. Vijayakumar, Vikram B. Suresh, S. Kundu

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引用次数: 11

Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing 用于高速扫描测试的时钟门控低发射WSA测试模式生成

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139132

Yi-Tsung Lin, Jiun-Lang Huang, X. Wen

引用次数: 4

Optimal manufacturing flow to determine minumum operating voltage 最佳生产流程，以确定最低工作电压

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139169

S. Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas

引用次数: 4

Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current 能够测量微安级电流的真正并行ATE的结构和实现

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139133

D. Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson

{"title":"Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current","authors":"D. Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson","doi":"10.1109/TEST.2011.6139133","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139133","url":null,"abstract":"With advancing technology nodes, the feature sizes of transistors are scaled down aggressively and the effects of process variations on semiconductor device parameters are becoming worse. Accurate device level statistical models are necessary to understand the composite effect of process variations on IC performance. Statistical models require a large amount of data from measurements made on wafers with test structures and product chips. High precision DC parametric measurements form a key component to understanding the device level process interactions. One important aspect of DC parametric measurements is the ability to accurately measure currents ranging from pico-amperes for leakage characterization to milli-amperes for transistor IV characterization. Sophisticated test equipment that meets the requirements of high accuracy and high throughput are needed for this purpose. In this paper we present a hybrid tester that addresses these requirements. The novel architecture presented here is scalable and truly parallel. The system is capable of measuring currents from pico-amperes to hundreds of milli-amperes and at the same time provide advanced digital test capabilities.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129160255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Test clock domain optimization for peak power supply noise reduction during scan 测试时钟域优化峰值电源噪声降低扫描期间

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139163

Jen-Yang Wen, Yu-Chuan Huang, M. Tsai, Kuan-Yu Liao, C. Li, M. Chang, Min-Hsiu Tsai, C. Tseng, Hung-Chun Li

引用次数: 2

Investigation into voltage and process variation-aware manufacturing test 电压和工艺变化感知制造试验的研究

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139138

B. Ingelsson

引用次数: 11

Pre-bond probing of TSVs in 3D stacked ICs 三维堆叠集成电路中tsv的键前探测

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139179

Brandon Noia, K. Chakrabarty

引用次数: 113

A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores 一种新的多孤立同芯故障诊断测试访问机制

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139171

Manish Sharma, Avijit Dutta, Wu-Tung Cheng, B. Benware, M. Kassab

引用次数: 22

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management DFT用于集成射频和电源管理的混合信号soc的极低成本测试

2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139128

Rajesh Mittal, Lakshmanan Balasubramanian, A. Sontakke, H. Parthasarathy, P. Narayanan, Puneet Sabbarwal, R. Parekhji

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引用次数: 5