{"title":"Physically-aware analysis of systematic defects in integrated circuits","authors":"W. Tam, R. D. Blanton","doi":"10.1109/MDT.2012.2211093","DOIUrl":"https://doi.org/10.1109/MDT.2012.2211093","url":null,"abstract":"Systematic defects due to design-process interactions are a significant component of integrated circuit (IC) yield loss in nano-scale technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that will affect a product over its manufacturing lifetime. This paper describes a comprehensive methodology that addresses the prevention and identification of systematic defects. For prevention, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of design-for-manufacturability (DFM) rules in preventing systematic defects that is based on volume diagnosis data. A second method called LASIC (Layout Analysis for Systematic Identification using Clustering), also based on volume diagnosis data, has been developed for identifying systematic defects that escape DFM. To validate RADAR and LASIC, a fast and accurate defect simulation framework called SLIDER (Simulation of Layout-Injected Defects for Electrical Responses) has been developed. SLIDER generates virtual failure data with known defect characteristics. Experiments involving two industrial chips and virtual failure data from SLIDER demonstrate the effectiveness of RADAR and LASIC.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114638439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu
{"title":"Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base","authors":"Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu","doi":"10.1109/TEST.2011.6139181","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139181","url":null,"abstract":"Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects for system chips that consist of multiple dies. In “2.5D” Stacked ICs (2.5D-SICs), multiple dies without TSVs are stacked side-by-side on top of a passive silicon interposer base containing TSVs. In true 3D-SICs, multiple dies containing TSVs themselves are vertically stacked; one or multiple of such stacks are possibly placed on a passive silicon interposer. This paper proposes a post-bond test and design-for-test (DfT) strategy for 2.5D- and 3D-SICs containing a passive silicon interposer base. Functional interconnects in the interposer are reused as much as possible in order to keep the interposer cost low.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115024939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using well/substrate bias manipulation to enhance voltage-test-based defect detection","authors":"A. Gattiker, P. Nigh","doi":"10.1109/TEST.2011.6139153","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139153","url":null,"abstract":"This paper proposes methods for taking advantage during voltage-based production test of the capability to control well and substrate (body) biases separately from the chip's VDD and GND. Such control is a by-product of a low-power design strategy that allows parts or all of the chip to go into low-power reduced-leakage states. The proposed test methods use body bias manipulation to increase or decrease transistor threshold voltages. Unlike related methods that rely on weakening transistors, the proposed methods are shown to enhance defect detectability by both weakening and strengthening transistors and by exploiting the ability to weaken/strengthen nfets/pfets separately.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127695422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power compression utilizing clock-gating","authors":"J. Rajski, Elham K. Moghaddam, S. Reddy","doi":"10.1109/TEST.2011.6139145","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139145","url":null,"abstract":"Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132376359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware hooks for transition scan characterization","authors":"P. Pant, Eric Skeels","doi":"10.1109/TEST.2011.6139166","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139166","url":null,"abstract":"Comprehensive transition scan content was deployed on an Intel® Itanium® server microprocessor design, including full coverage patterns for all core logic blocks. Since this was the first time at-speed scan patterns were being planned as a manufacturing screen on an Intel® CPU core design, the test deployment team needed to ensure that all concerns of over-and under-testing were systematically addressed. A few innovative and novel DFT solutions were deployed to ensure that the post-silicon team had the adequate tools to fully analyze the at-speed scan content. This paper describes these DFT solutions that proved invaluable during this process.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130524440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Actual implementation of multi domain test: Further reduction of cost of test","authors":"Yasuhiro Takahashi, A. Maeda, Mitsuhiro Ogura","doi":"10.1109/TEST.2011.6139135","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139135","url":null,"abstract":"Multi-Sites Test is the popular way to reduce the cost-of-test (COT) at the wafer and the final test. Limitations exist, however, such as the low Multi-Site Efficiency of analog mixed signal tests and the high system price for large pin count devices. Concurrent Test has been implemented to reduce the test time. This test strategy is difficult to implement without the DFT design of the device. The authors introduced the concept of Multi-Domain Test at VTS 2011 and explained that this Multi-Domain Test solves the aforementioned problems and limitations of Multi-Site Test and Concurrent Test. The authors also showed that the COT of Multi-Domain Test is lower than that of Multi-Site Test for high-end SOC devices. This Multi-Domain Test was applied to a mixed signal SOC. Although the Multi-Site Efficiency of the Dual-Site Test was more than 97%, the COT of the Dual-Domain Test was approximately 10% lower than that of the Dual-Site Test.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128802274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IEEE Std 1581 — A standardized test access methodology for memory devices","authors":"H. Ehrenberg, Bob Russell","doi":"10.1109/TEST.2011.6139141","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139141","url":null,"abstract":"Memory devices have been becoming more complex with every generation and this trend is very likely to continue. Different kinds of memories present different challenges for board level test applications. In this paper we discuss several of those challenges and will introduce a new test technology standardized as IEEE Std 1581, offering an elegant solution to many problems related to the test of the board and system level connectivity at memory device pins.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takahiro J. Yamaguchi, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, K. Asada, M. Abbas, S. Komatsu
{"title":"Application of a continuous-time level crossing quantization method for timing noise measurements","authors":"Takahiro J. Yamaguchi, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, K. Asada, M. Abbas, S. Komatsu","doi":"10.1109/TEST.2011.6139177","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139177","url":null,"abstract":"This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the underlying theory of the performance measurement of an LCADC is also included.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127696319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhaobo Zhang, K. Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu
{"title":"Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks","authors":"Zhaobo Zhang, K. Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu","doi":"10.1109/TEST.2011.6139139","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139139","url":null,"abstract":"Diagnosis of functional failures at the board level is critical for improving product yield and reducing manufacturing cost. State-of-the-art board-level diagnostic software is unable to cope with high complexity and ever-increasing clock frequencies, and the identification of the root cause of failure on a board is a major problem today. Ambiguous or incorrect repair suggestions lead to long debug times and even wrong repair actions, which significantly increases the repair cost and adversely impacts yield. We propose a smart diagnosis method based on artificial neural networks that can learn from repair history and accurately localize the root cause of a failure. Fine-grained fault syndromes extracted from failure logs and the corresponding repair actions are used to train the neural network. The proposed network structure is simple, it can be rapidly trained, and it is scalable to large datasets. Moreover, the relationship between typical syndromes and the most appropriate repair actions can be easily inferred from the network structure. An industrial board, which is currently in production, is used to validate the diagnosis approach in terms of diagnostic accuracy, resolution, and quantifiable improvement over current diagnostic software.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"13 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131575347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Hapke, J. Schlöffel, W. Redemund, Andreas Glowatz, J. Rajski, Michael Reese, J. Rearick, J. Rivers
{"title":"Cell-aware analysis for small-delay effects and production test results from different fault models","authors":"F. Hapke, J. Schlöffel, W. Redemund, Andreas Glowatz, J. Rajski, Michael Reese, J. Rearick, J. Rivers","doi":"10.1109/TEST.2011.6139151","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139151","url":null,"abstract":"This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}