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2011 IEEE International Test Conference最新文献

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Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal 优雅的SSC结构通过AWG实现信号，并对宽带信号进行有组织的欠采样
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139159
H. Okawara
{"title":"Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal","authors":"H. Okawara","doi":"10.1109/TEST.2011.6139159","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139159","url":null,"abstract":"Implementing a SSC (Spread Spectrum Clocking) solution is not an easy task for digital resources to generate and analyze. In contrast, analog resources in mixed signal testers can easily take care of such signals. The purpose of this work is to establish organized methodologies to generate and analyze the SSC implemented signal by using an AWG (Arbitrary Waveform Generator) and a waveform sampler. The first section describes the FFT (Fast Fourier Transform) & IFFT (Inverse FFT) method which provides an elegant method to construct a SSC high-speed digital data stream using an AWG. The second section describes an under-sampling method to analyze wideband signals such as a SSC high-speed digital signal by using a waveform sampler. A practical example shows a data stream of a 1.5Gbps SATA (Serial ATA) with a 30ms triangle profile SSC period.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115003287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Deterministic IDDQ diagnosis using a net activation based model 基于网络激活模型的IDDQ确定性诊断
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139175
Andras Kun, R. Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng
{"title":"Deterministic IDDQ diagnosis using a net activation based model","authors":"Andras Kun, R. Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng","doi":"10.1109/TEST.2011.6139175","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139175","url":null,"abstract":"In Automotive business, the quiescent supply current test (IDDQ) is a widely used and valuable test method to screen out production failures and reach the required low defective parts per million (DPPM) quality targets. Automatic Test Pattern Generation (ATPG) tools can generate scan based IDDQ patterns with high test coverage for Pseudo Stuck-At (PSA) faults. Functional pass but IDDQ failing devices need to be diagnosed for various purposes. In this paper a fast simulation based method is proposed to diagnose IDDQ failures with single or multiple defects for digital circuitry. The results are verified on real silicon for several 130nm Automotive designs. Furthermore automation of the diagnosis method for high volume diagnosis similar to scan volume diagnosis is shown in the paper outlook.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116883845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Die-level adaptive test: Real-time test reordering and elimination 模级自适应测试:实时测试重新排序和淘汰
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139173
Kapil R. Gotkhindikar, W. R. Daasch, K. Butler, J. Carulli, A. Nahar
{"title":"Die-level adaptive test: Real-time test reordering and elimination","authors":"Kapil R. Gotkhindikar, W. R. Daasch, K. Butler, J. Carulli, A. Nahar","doi":"10.1109/TEST.2011.6139173","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139173","url":null,"abstract":"This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering and elimination is based on statistics of these predicted fail rates and is naturally monitored by a wafer based reset. Wafer sort test response data for two 65nm integrated circuit products is used to demonstrate this method. Test time reductions of about 30% are achieved with quality levels within industry expectations.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114563241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Partial state monitoring for fault detection estimation 局部状态监测用于故障检测估计
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139146
Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak
{"title":"Partial state monitoring for fault detection estimation","authors":"Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak","doi":"10.1109/TEST.2011.6139146","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139146","url":null,"abstract":"Obtaining fault coverage information for functional input sequences is often very difficult. Although many simulation-based techniques have been proposed, they are generally computationally expensive, and if the input sequence changes, new expensive simulations must be run. In this paper, we propose a new type of hardware monitor for the probabilistic determination of how many times a fault was likely to have been covered during functional test or program execution. In addition to providing coverage information for functional test sequences — even those that have never been simulated — these monitors can also be used to determine the relative criticality of faults for the applications a user is running in real time. Thus, in the future, this method has the potential to provide new dynamic optimization capabilities for on-chip field testing.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122734308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism 具有模式无关测试访问机制的SoC设计中的EDT信道带宽管理
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139170
Jakub Janicki, J. Tyszer, Avijit Dutta, M. Kassab, Grzegorz Mrugalski, N. Mukherjee, J. Rajski
{"title":"EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism","authors":"Jakub Janicki, J. Tyszer, Avijit Dutta, M. Kassab, Grzegorz Mrugalski, N. Mukherjee, J. Rajski","doi":"10.1109/TEST.2011.6139170","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139170","url":null,"abstract":"The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127801184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Defect Oriented Testing for analog/mixed-signal devices 模拟/混合信号设备的缺陷导向测试
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139127
B. Kruseman, B. Tasic, C. Hora, J. Dohmen, H. Hashempour, M. V. Beurden, Y. Xing
{"title":"Defect Oriented Testing for analog/mixed-signal devices","authors":"B. Kruseman, B. Tasic, C. Hora, J. Dohmen, H. Hashempour, M. V. Beurden, Y. Xing","doi":"10.1109/TEST.2011.6139127","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139127","url":null,"abstract":"We present an application of Defect Oriented Testing (DOT) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, and test selection. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup of over 100x in the DOT process. Moreover, a number of methods are presented to improve the accuracy of this algorithm. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the analyzed production tests of the device can be reduced by at least 50%.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A novel robust and accurate spectral testing method for non-coherent sampling 一种新的鲁棒和精确的非相干采样光谱测试方法
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139176
Siva Sudani, Minshun Wu, Degang Chen
{"title":"A novel robust and accurate spectral testing method for non-coherent sampling","authors":"Siva Sudani, Minshun Wu, Degang Chen","doi":"10.1109/TEST.2011.6139176","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139176","url":null,"abstract":"Spectral testing is one of the frequently encountered problems in signal processing and communications. It is a challenging task to obtain coherent sampling for accurate spectral testing. Windowing techniques are widely used to perform spectral testing when the sampling is slightly noncoherent. This paper proposes a new Fundamental Identification and Replacement (FIR) method. The proposed method can estimate the spectral characteristics accurately without requiring coherent sampling. The method is robust to any level of non-coherency, which makes on-chip spectral testing possible. The new method is computationally efficient and is applicable for high resolution spectral testing. Furthermore, the proposed method can perform both single tone signal test and multiple tone signal test accurately. The method gives accurate results even in situations when the windowing techniques cannot give correct results. Simulation results show the robustness and the computational efficiency of the proposed method. The method is also validated with the experimental data.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122338508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan 基于标准边界扫描的高速并行I/ o自适应参数BIST
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139165
S. Sunter, A. Roy
{"title":"Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan","authors":"S. Sunter, A. Roy","doi":"10.1109/TEST.2011.6139165","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139165","url":null,"abstract":"An I/O BIST with calibrated 50 ps delay measurement resolution, presented at ITC'10, requires no changes to 1149.1 boundary scan cells nor the I/O cells they access, and avoids using delay cells or delay matching. In this paper, we describe how we improved the silicon-proven resolution by 10X (to 5 ps) without limiting the delay range. The finer resolution enables measurement of crosstalk between I/Os, which is a known source of jitter — we provide results measured on an FPGA. We also describe three new tests (for duty cycle, slew rate, and skew) that unobtrusively test I/O parameters while high-speed data from core logic is being transmitted on DDR pins (or USB2). Lastly, we describe how adaptive test limits are applied by setting limits on-chip relative to the average value measured for any selected group of pins on each device.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Surviving state disruptions caused by test: A case study 由测试引起的状态中断:一个案例研究
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139140
K. Parker, S. Kameyama, David Dubberke
{"title":"Surviving state disruptions caused by test: A case study","authors":"K. Parker, S. Kameyama, David Dubberke","doi":"10.1109/TEST.2011.6139140","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139140","url":null,"abstract":"The practice of initializing a board or system for testing purposes is not an exact science, but rather, pursued empirically and with an increasing risk of undesired side effects. It has been suspected that Boundary-Scan testing can cause such side effects. This paper provides a case study of such a board where a detailed root-cause analysis was performed. Some issues are identified that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing and to leave it in a safe state upon completion of testing.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126721944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Forward prediction based on wafer sort data — A case study 基于晶圆分选数据的正向预测-一个案例研究
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139174
N. Sumikawa, D. Drmanac, Li-C. Wang, L. Winemberg, M. Abadir
{"title":"Forward prediction based on wafer sort data — A case study","authors":"N. Sumikawa, D. Drmanac, Li-C. Wang, L. Winemberg, M. Abadir","doi":"10.1109/TEST.2011.6139174","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139174","url":null,"abstract":"This paper studies the potential of using wafer probe tests to predict the outcome of future tests. The study is carried out using test data based on an SoC design for the automotive market. Given a set of known failing parts, there are two possible approaches to learn. First a single binary classification model can be learned to model all failing parts. We show that this approach can be effective if the failing parts are compatible in learning. Second, an individual outlier model can be learned for each failing part. We show that this approach is suitable for learning failing parts such as customer returns, where each may have a unique failing behavior. We also show that with Principal Component Analysis (PCA), a learning model can be visualized in two or three dimensional PC space, which facilitates an engineer to manually select or adjust the model.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"91 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120924712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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