{"title":"Generic, orthogonal and low-cost March Element based memory BIST","authors":"A. V. Goor, S. Hamdioui, H. Kukner","doi":"10.1109/TEST.2011.6139148","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139148","url":null,"abstract":"This paper contributes to the field of MBIST architecture and implementation by addressing the two most area-critical components: the Command Memory (ComMem) and the Address Generator (AddrGen). The ComMem area is minimized by using a novel MBIST architecture, based on the Generic March Element (GME) concept. A GME is a March Element which specifies the required operations and the generic data values; it can be specified independent of the algorithm stresses. The AddrGen area is minimized by using an efficient implementation, based on a single Up-counter and a set of multiplexors. The experimental results show that the proposed MBIST outperforms the existing MBISTs in terms of area, power, speed, and flexibility. E.g., for a 16Kx16-bit memory, the proposed MBIST consumes about 40% less area and operates at least 1.6 times faster than the state-of-the art.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123322672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Banerjee, Shreyas Sen, S. Devarakond, A. Chatterjee
{"title":"Accurate signature driven power conscious tuning of RF systems using hierarchical performance models","authors":"A. Banerjee, Shreyas Sen, S. Devarakond, A. Chatterjee","doi":"10.1109/TEST.2011.6139144","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139144","url":null,"abstract":"In this research, a new post-manufacture tuning approach for yield improvement of advanced RF systems is developed. The proposed method first determines module level performances from the system level response (signature) to an applied RF diagnostic test using top-down model diagnosis. Then a constrained optimizer is used to determine the best module level tuning parameter values that satisfy system level specifications (bottom-up analysis) based on the determined performances of the individual modules in a power-conscious manner. Both top-down and bottom-up analysis techniques are supported by hierarchical RF behavioral models. The health (effects of process variations) of individual modules affects the relationship between module level tuning parameters and module level performance metrics and is factored into the tuning procedure. A key benefit of the proposed approach is that only a single test application is needed. Simulation results and hardware data prove the efficiency of the proposed tuning technique.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131566557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Online timing variation tolerance for digital integrated circuits","authors":"Guihai Yan, Xiaowei Li","doi":"10.1109/TEST.2011.6139136","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139136","url":null,"abstract":"Ensuring safe timing increasingly becomes a paramount challenge with the technology scaling to nanoscale. This study aims to provide timing variation detection and tolerance solutions. We first propose a versatile online timing variation detection scheme which can handle multiple types of faults. With the capability of detection, we further propose two tolerance schemes to eliminate runtime margin in DVFS applications and improve lifetime reliability under progressive aging mechanisms, respectively. Lastly, given the more complicated PVT variations whose primary circuit implication is also timing variations, we propose TEA-TM, a novel architectural scheme to reduce timing emergencies. Collectively, we aims to build a comprehensive framework for timing variation tolerance and demonstrate several s pec ific applications.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125326956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wafer probe test cost reduction of an RF/A device by automatic testset minimization — A case study","authors":"D. Drmanac, M. Laisne","doi":"10.1109/TEST.2011.6139143","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139143","url":null,"abstract":"This work presents a case study of wafer probe test cost reduction by multivariate parametric testset optimization for a production RF/A device. More than 1.5 million tested device samples across dozens lots and hundreds of parametric measurements are analyzed using a new automatic testset minimization system. Parametric test subsets are found that can be used to predict infrequent wafer probe failures. Multivariate test models are generated to justify removal of ineffective tests, screen failures with minimal test cost, and demonstrate that some frequently passing tests are safe drop candidates. The proposed method is evaluated using parametric test data from an RF/A IC currently in production, showing how to reduce test cost and uncover tradeoffs between test escapes and overkills during high volume wafer probe screening.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133253765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ishida, K. Ichiyama, D. Watanabe, M. Kawabata, T. Okayasu
{"title":"Real-time testing method for 16 Gbps 4-PAM signal interface","authors":"M. Ishida, K. Ichiyama, D. Watanabe, M. Kawabata, T. Okayasu","doi":"10.1109/TEST.2011.6139160","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139160","url":null,"abstract":"This paper proposes a method for testing a device with multi-level signal interfaces. This method utilizes multi-level drivers that generate multi-level signals and multi-level comparators that are based on a new concept. The multi-level drivers can test the voltage noise tolerance of a receiver device with multi-level signal interfaces. The multi-level comparators realize real-time functional testing of a multi-level signal with the same number of comparators as a conventional test system, by changing the threshold voltage levels dynamically in response to the expected values of a signal under test. This dynamic threshold comparator concept is suitable for a system testing a high-speed multi-level signal. This method is also scalable for an increase in the number of voltage levels such as 8-PAM and 16-PA M signals. In addition, with the proposed method, the testing of a signal having emphasis/ de-emphasis can be realized, and improved testing of the digital modulation signal such as by QAM can be expected. Experimental results are discussed with a prototype circuit that demonstrates the proposed concept applied to a 16 Gbps 4-PAM Test System. Applications of the proposed method are also discussed.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}