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2011 IEEE International Test Conference最新文献

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End-to-end error correction and online diagnosis for on-chip networks 片上网络的端到端纠错和在线诊断
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139156
S. Shamshiri, A. Ghofrani, K. Cheng
{"title":"End-to-end error correction and online diagnosis for on-chip networks","authors":"S. Shamshiri, A. Ghofrani, K. Cheng","doi":"10.1109/TEST.2011.6139156","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139156","url":null,"abstract":"We propose a comprehensive solution for end-to-end (e2e) error correction and online defect diagnosis for on-chip networks. For e2e error correction, we propose an interleaved error-locality-aware code that efficiently corrects both random and burst errors. We demonstrate that for 64-bit wide network links, interleaving four of the proposed code, 2G4L(26,16), each of which supports 16bit data, can correct as many as two random errors or 16 adjacent errors. In order to maintain the error correction capability of the Error Correcting Code (ECC) for transient and intermittent errors, we further propose an e2e data gathering and online diagnosis approach that locates the defective wires and replaces them with the spare wires embedded in the network. Our analytical and experimental studies show that under heavy noise, high escape rate, uncertainty about routing, and many other harmful effects, the diagnostic data collected by the proposed approach are accurate enough for the purpose of passive diagnosis.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125522623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
Adaptive multidimensional outlier analysis for analog and mixed signal circuits 模拟和混合信号电路的自适应多维离群分析
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139178
E. Yilmaz, S. Ozev, K. Butler
{"title":"Adaptive multidimensional outlier analysis for analog and mixed signal circuits","authors":"E. Yilmaz, S. Ozev, K. Butler","doi":"10.1109/TEST.2011.6139178","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139178","url":null,"abstract":"Outlier devices behave differently from the majority of the devices and are considered to be potentially defective. Identifying outliers has many applications in test, including defect filters for alternate test, and setting pass/fail limits for automotive domain. In previous work, outliers have been identified using single dimensional and/or static methods which does not exploit information efficiently. In this work, we propose an adaptive multidimensional outlier analysis method that combines the information of multiple measurement parameters and judiciously selects only information rich parameters to maximize detection probability. Furthermore, the proposed method continously updates to track process shift to enable adaptation to the evolving processes. The proposed method can be integrated within an existing test framework to improve test quality with little or no additional test time cost. In this context, we integrate our technique with an adaptive test framework and show that the method enables improved test quality.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116977842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Design-for-debug layout adjustment for FIB probing and circuit editing 为调试而设计的FIB探测和电路编辑布局调整
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139155
K. Chen, Tsung-Wei Chang, Meng-Chen Wu, M. Chao, Jing-Yang Jou, Sonair Chen
{"title":"Design-for-debug layout adjustment for FIB probing and circuit editing","authors":"K. Chen, Tsung-Wei Chang, Meng-Chen Wu, M. Chao, Jing-Yang Jou, Sonair Chen","doi":"10.1109/TEST.2011.6139155","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139155","url":null,"abstract":"While the technology node continually and aggressively scales, the resolution of FIB techniques does not scale as fast. Thus, the percentage of nets which can be observed or repaired through FIB probing or circuit editing is significantly decreased for advanced process technologies, which limits the candidates that can be physically examined through the FIB techniques during the debugging process. This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals. The layout adjustment is made through pre-defined simple operations subject to the design rules and the timing constraints. Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool. The experimental result based on an 90nm technology has demonstrated that the proposed DFD framework can effectively increase the FIB observable and repairable rates under different parameter settings while the overall area and circuit performance remain the same.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121932497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
State of the art low capture power methodology 最先进的低捕获功率方法
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139164
Swapnil Bahl, R. Mattiuzzo, Shray Khullar, A. Garg, S. Graniello, Khader S. Abdel-Hafez, S. Talluto
{"title":"State of the art low capture power methodology","authors":"Swapnil Bahl, R. Mattiuzzo, Shray Khullar, A. Garg, S. Graniello, Khader S. Abdel-Hafez, S. Talluto","doi":"10.1109/TEST.2011.6139164","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139164","url":null,"abstract":"Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today's power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126201830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A novel scan segmentation design method for avoiding shift timing failure in scan testing 一种避免扫描测试中移位时序失效的扫描分割设计新方法
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139162
Yuta Yamato, X. Wen, M. Kochte, K. Miyase, S. Kajihara, Laung-Terng Wang
{"title":"A novel scan segmentation design method for avoiding shift timing failure in scan testing","authors":"Yuta Yamato, X. Wen, M. Kochte, K. Miyase, S. Kajihara, Laung-Terng Wang","doi":"10.1109/TEST.2011.6139162","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139162","url":null,"abstract":"High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132453959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Logic BIST silicon debug and volume diagnosis methodology 逻辑BIST硅调试和体积诊断方法
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139147
M. E. Amyeen, A. Jayalakshmi, S. Venkataraman, Sundar V. Pathy, E. C. Tan
{"title":"Logic BIST silicon debug and volume diagnosis methodology","authors":"M. E. Amyeen, A. Jayalakshmi, S. Venkataraman, Sundar V. Pathy, E. C. Tan","doi":"10.1109/TEST.2011.6139147","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139147","url":null,"abstract":"Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST production fail volume diagnosis and presented tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis. Results are presented showing successful isolation of silicon speed-paths on Intel® SOCs.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131677930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Faster-than-at-speed test for increased test quality and in-field reliability 更快的速度测试，提高测试质量和现场可靠性
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139131
T. Yoneda, Keigo Hori, M. Inoue, H. Fujiwara
{"title":"Faster-than-at-speed test for increased test quality and in-field reliability","authors":"T. Yoneda, Keigo Hori, M. Inoue, H. Fujiwara","doi":"10.1109/TEST.2011.6139131","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139131","url":null,"abstract":"Faster-than-at-speed testing is an effective approach to screen small delay defects (SDDs) and increase test quality and in-field reliability. This paper presents a novel framework of faster-than-at-speed test to minimize the slack of the sensitized path for each fault. The basic strategy is to use multiple faster-than-at-speed test timings with endpoint masking for each pattern. By performing a detailed analysis of the sensitized path delay for active faults and active endpoints in each pattern, we can minimize the slack for the detectable faults while preventing a large increase in pattern count. We also present methods to maximize the sensitized path delay and further reduce the pattern count under a constraint on the allowable slack size, instead of minimizing the slack. Experimental results for ITC'99 benchmark circuits show the effectiveness of the proposed methods in terms of slack size and sensitized path delay for detectable faults, statistical delay quality level (SDQL) and pattern count.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"57 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134034235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Test cost reduction through performance prediction using virtual probe 利用虚拟探针进行性能预测，降低测试成本
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139129
Hsiu-Ming Chang, K. Cheng, Wangyang Zhang, Xin Li, K. Butler
{"title":"Test cost reduction through performance prediction using virtual probe","authors":"Hsiu-Ming Chang, K. Cheng, Wangyang Zhang, Xin Li, K. Butler","doi":"10.1109/TEST.2011.6139129","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139129","url":null,"abstract":"The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on their statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with more than 50 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. In this example, the 3σ error of VP prediction is less than 12% for predictable or highly predictable test items. Applying the VP technique can on average replace 59% of test measurement by prediction and, consequently, reduce the overall test time by 57.6%.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124749532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
P-PET: Partial pseudo-exhaustive test for high defect coverage P-PET:高缺陷覆盖率的部分伪彻底测试
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139130
A. Mumtaz, M. Imhof, H. Wunderlich
{"title":"P-PET: Partial pseudo-exhaustive test for high defect coverage","authors":"A. Mumtaz, M. Imhof, H. Wunderlich","doi":"10.1109/TEST.2011.6139130","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139130","url":null,"abstract":"Pattern generation for embedded testing often consists of a phase generating random patterns and a second phase where deterministic patterns are applied. This paper presents a method which optimizes the first phase significantly and increases the defect coverage, while reducing the number of deterministic patterns required in the second phase. The method is based on the concept of pseudo-exhaustive testing (PET), which was proposed as a method for fault model independent testing with high defect coverage. As its test length can grow exponentially with the circuit size, an application to larger circuits is usually impractical. In this paper, partial pseudo-exhaustive testing (P-PET) is presented as a synthesis technique for multiple polynomial feedback shift registers. It scales with actual technology and is comparable with the usual pseudo-random (PR) pattern testing regarding test costs and test application time. The advantages with respect to the defect coverage, N-detectability for stuck-at faults and the reduction of deterministic test lengths are shown using state-of-the art industrial circuits.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Multi-function multi-GHz ATE extension using state-of-the-art FPGAs 使用最先进的fpga的多功能多ghz ATE扩展
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139161
A. Majid, D. Keezer
{"title":"Multi-function multi-GHz ATE extension using state-of-the-art FPGAs","authors":"A. Majid, D. Keezer","doi":"10.1109/TEST.2011.6139161","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139161","url":null,"abstract":"This paper presents a multi-function multi-GHz test module designed to enhance the performance capabilities of automatic test equipment (ATE). The test module is designed with a core logic block consisting of a high-performance FPGA. It also contains an application specific logic block that is designed to perform multiple functions not possible with the FPGA alone. We demonstrate five applications: high-speed signal multiplexing up to 16Gbps, loopback testing, jitter injection, amplitude adjustment, and timing adjustment. The loopback path allows testing up to 9.28Gbps. Digital timing adjustment up to 10ns in 10ps increments, and fine adjustment up to 61ps is shown. Jitter injection up to 81ps (p-p) and amplitude adjustment over a range of 600mV are demonstrated. The core logic block itself has capabilities to generate 10Gbps output signals with 38ps (p-p, BER = 2×10−5) jitter. The test module is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). A bypass option allows signals from the ATE to pass through to the DUT, permitting use of traditional ATE functions.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123052102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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