2011 IEEE International Test Conference最新文献

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Transition test bring-up and diagnosis on UltraSPARCTM processors UltraSPARCTM处理器的过渡试验提出与诊断
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139167
Liang-Chi Chen, P. Dahlgren, P. Dickinson, S. Davidson
{"title":"Transition test bring-up and diagnosis on UltraSPARCTM processors","authors":"Liang-Chi Chen, P. Dahlgren, P. Dickinson, S. Davidson","doi":"10.1109/TEST.2011.6139167","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139167","url":null,"abstract":"We describe methods to use PLL-based transition test in support of chip bring-up. We used it to diagnose slow paths for performance improvement. During bring-up, often the issues of setup, design, scan patterns, and silicon slow paths are mixed together, making diagnosis more difficult. We discuss techniques used to understand and resolve these issues, and show examples of the benefit of transition test over functional and system test.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130784451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analyzing ATE interconnect performance for serial links of 10 Gbps and above 分析10gbps及以上串行链路的ATE互连性能
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139158
Mitchell Lin, T. Tolman
{"title":"Analyzing ATE interconnect performance for serial links of 10 Gbps and above","authors":"Mitchell Lin, T. Tolman","doi":"10.1109/TEST.2011.6139158","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139158","url":null,"abstract":"This paper describes a method for analyzing the performance of Automatic Test Equipment (ATE) Device Interface Boards (DIB) for High-Speed Serial Link interface. The procedure requires using only the device under test (DUT) to generate known PRBS TX data and an ATE digitizer to capture the waveform. The information of impulse and frequency response of the signal path can then be obtained by processing this waveform. In addition, data-dependent and periodic jitter can also be calculated. Therefore, without the use of other sophisticated hardware setup, this approach can validate the performance of the fixtures required for testing 10 Gbps Serial Link interfaces and help to identify any signal integrity issues. The proposed method can process waveform data from any instrument and, therefore, can be exploited to analyze signals above 10 Gbps, being limited only by the bandwidth of the instrument itself.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125129067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient combination of trace and scan signals for post silicon validation and debug 跟踪和扫描信号的有效组合后硅验证和调试
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139157
K. Basu, P. Mishra, Priyadarsan Patra
{"title":"Efficient combination of trace and scan signals for post silicon validation and debug","authors":"K. Basu, P. Mishra, Priyadarsan Patra","doi":"10.1109/TEST.2011.6139157","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139157","url":null,"abstract":"Post-silicon validation is as an important aspect of any integrated circuit design methodology. The primary objective is to capture the bugs that have escaped the pre-silicon validation phase. A major challenge in post-silicon debug is the limited observability of internal signals in the circuit. Recent technological advances, such as embedded logic analysis, allow to store some signal states in a trace buffer. A promising direction to improve observability is to combine a small set of signals traced every cycle with a large set of scan signals stored across several cycles. The limited size of the trace buffer constrains the number of trace and scan signals that can be stored. In this paper, we propose an efficient algorithm to select a profitable combination of trace and scan signals to maximize the overall signal restoration performance. Our experimental results using ISCAS'89 benchmarks demonstrate that our approach can improve the signal restoration by 17% compared to the existing techniques.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124175345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Evaluation of TSV and micro-bump probing for wide I/O testing 宽I/O测试中TSV和微碰撞探测的评价
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139180
Ken Smith, P. Hanaway, Mike Jolley, R. Gleason, E. Strid, T. Daenen, L. Dupas, B. Knuts, E. Marinissen, M. V. Dievel
{"title":"Evaluation of TSV and micro-bump probing for wide I/O testing","authors":"Ken Smith, P. Hanaway, Mike Jolley, R. Gleason, E. Strid, T. Daenen, L. Dupas, B. Knuts, E. Marinissen, M. V. Dievel","doi":"10.1109/TEST.2011.6139180","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139180","url":null,"abstract":"Practical silicon stacking requires pre-tested dies, but contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards have achieved. This paper examines a cost-effective, lithographic-based MEMS probe card technology that is suitable for probing 40µm pitch arrays, and scalable to finer pitches. Initial mechanical and electrical results are presented, demonstrating the feasibility of probing large arrays at 1 gram-force per tip with very low pad damage, so as not to impair downstream bonding or other processing steps.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124360808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Multi-site test of RF transceivers on low-cost digital ATE 射频收发器在低成本数字ATE上的多站点测试
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139142
Ivo Koren, Ben Schuffenhauer, F. Demmerle, Frank Neugebauer, Gert Pfahl, D. Rautmann
{"title":"Multi-site test of RF transceivers on low-cost digital ATE","authors":"Ivo Koren, Ben Schuffenhauer, F. Demmerle, Frank Neugebauer, Gert Pfahl, D. Rautmann","doi":"10.1109/TEST.2011.6139142","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139142","url":null,"abstract":"In this paper we present a concept and its implementation for the productive quad-site test of a state-of-the-art 2G/3G RF transceiver device on a low-cost purely digital ATE. Our approach is based on calibrated reference RF transceiver device used as a compact, low-cost RF signal source and RF measurement instrument. The reference device along with supporting analog and digital circuitry for pattern control and test data handling is placed on PCB modules plugged on-top the test DUT board one for each site. The design of the modules, the DUT boards and the software is explained in the context of mass production, and measurement results are given.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122663031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
On using address scrambling to implement defect tolerance in SRAMs 利用地址置乱实现ram缺陷容错
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139149
R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine
{"title":"On using address scrambling to implement defect tolerance in SRAMs","authors":"R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine","doi":"10.1109/TEST.2011.6139149","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139149","url":null,"abstract":"This paper proposes an innovative approach to cope with defects in SRAM bit-cell array. Traditional approaches use spare parts (rows, columns or blocks) to replace defective bit-cells. Instead of replacing defective bit-cells, we propose to operate the SRAM with reduced storage capacity whenever defective bit-cells are present. We implement this feature through a programmable combinational logic, called Scrambling Module (SM), which scrambles the memory addresses. The scrambling changes the addresses of the defective bit-cells, grouping them in an idle address zone located at the end of the memory address plan. The SM is described by using a mathematical formulation based on linear algebra. The proposed technique can be used in combination with traditional redundancy approaches using spare rows and/or columns. The effectiveness of three different SM is demonstrated, considering a 1MBit SRAM. For a given level of defect tolerance, it is shown that our technique can reduce the amount of spare area by several orders of magnitude. Moreover, as the SM is implemented as an external block, it does not affect the maximum operation frequency of the SRAM. Instead, it affects the memory access delay.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test access and the testability features of the Poulson multi-core Intel Itanium® processor 测试访问和Poulson多核Intel Itanium®处理器的可测试性功能
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139168
D. Bhavsar, Steve Poehlman
{"title":"Test access and the testability features of the Poulson multi-core Intel Itanium® processor","authors":"D. Bhavsar, Steve Poehlman","doi":"10.1109/TEST.2011.6139168","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139168","url":null,"abstract":"This paper presents the “t-Ring” based DFX access architecture and the testability features of Intel's latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models in high volume manufacturing test and debug platforms.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115473758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Software-Based Self-Test methodology for on-line testing of processor caches 一种基于软件的处理器缓存在线自检方法
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139154
G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos
{"title":"A Software-Based Self-Test methodology for on-line testing of processor caches","authors":"G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos","doi":"10.1109/TEST.2011.6139154","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139154","url":null,"abstract":"Nowadays, on-line testing is essential for modern high-density microprocessors to detect either latent hardware defects or new defects appearing during lifetime both in logic and memory modules. For cache arrays, the flexibility to apply online different March tests is a critical requirement. For small memory arrays that may lack programmable Memory Built-In Self-Test (MBIST) circuitry, such as L1 cache arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for online periodic testing of L1 data and instruction cache, both for tag and data arrays. The proposed SBST methodology utilizes existing special purpose instructions that modern Instruction Set Architectures (ISAs) implement to access caches for debug-diagnostic and performance purposes, termed hereafter Direct Cache Access (DCA) instructions, as well as, performance monitoring mechanisms to overcome testability challenges. The methodology has been applied to 2 processor benchmarks, OpenRISC and LEON3 to demonstrate its high adaptability, and experimental comparison results against previous contributions show that the utilization of DCA instructions significantly improves test code size (83%) and test duration (72%) when applied to the same benchmark (LEON3).","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127016739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Development of an ATE test cell for at-speed characterization and production testing 开发用于高速特性和生产测试的ATE测试单元
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139134
J. Moreira
{"title":"Development of an ATE test cell for at-speed characterization and production testing","authors":"J. Moreira","doi":"10.1109/TEST.2011.6139134","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139134","url":null,"abstract":"This paper describes the development of a test cell intended for thorough characterization and production testing of a complex multigigabit IC. The objective of this project was to provide a straightforward way to transition from characterization testing to the early production ramp with minimal effort while at the same time not restricting or limiting thorough characterization of the IC. This included providing the flexibility for the Test Engineer being able to use any external measurement instrument required for characterizing the DUT.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Techniques to improve memory interface test quality for complex SoCs 提高复杂soc内存接口测试质量的技术
2011 IEEE International Test Conference Pub Date : 2011-09-01 DOI: 10.1109/TEST.2011.6139172
V. Devanathan, S. Vooka
{"title":"Techniques to improve memory interface test quality for complex SoCs","authors":"V. Devanathan, S. Vooka","doi":"10.1109/TEST.2011.6139172","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139172","url":null,"abstract":"Aggressive speed and voltage binning schemes are widely used in the industry to improve the yield of SoCs. For accurate bin classification, it is essential that the tests used for binning target the worst critical/speed-limiting paths in the design. We have observed in many SoCs that memory interface paths are amongst the top critical paths. In this paper, we propose new DFT schemes to improve the quality of memory interface logic test. We also discuss practical challenges and propose solutions for successfully implementing ATPG on memory-interface paths of large SoCs. Experimental results on 40nm industrial designs show an average increase of 36% memory interface fault coverage. Fmax result from production SoC silicon establishes the effectiveness of the proposed scheme for speed binning.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117205099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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