Test access and the testability features of the Poulson multi-core Intel Itanium® processor

D. Bhavsar, Steve Poehlman
{"title":"Test access and the testability features of the Poulson multi-core Intel Itanium® processor","authors":"D. Bhavsar, Steve Poehlman","doi":"10.1109/TEST.2011.6139168","DOIUrl":null,"url":null,"abstract":"This paper presents the “t-Ring” based DFX access architecture and the testability features of Intel's latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models in high volume manufacturing test and debug platforms.","PeriodicalId":260931,"journal":{"name":"2011 IEEE International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2011.6139168","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

This paper presents the “t-Ring” based DFX access architecture and the testability features of Intel's latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models in high volume manufacturing test and debug platforms.
测试访问和Poulson多核Intel Itanium®处理器的可测试性功能
本文介绍了基于“t-Ring”的DFX访问架构和英特尔最新的多核Itanium®处理器的可测试性特性。该架构使用独特和创新的解决方案解决了测试多核CPU的许多常见挑战。该体系结构的核心是一个分层和可伸缩的测试访问机制设计,为大批量制造测试和调试平台中的各种使用模型提供灵活的访问。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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