Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current

Abstract

With advancing technology nodes, the feature sizes of transistors are scaled down aggressively and the effects of process variations on semiconductor device parameters are becoming worse. Accurate device level statistical models are necessary to understand the composite effect of process variations on IC performance. Statistical models require a large amount of data from measurements made on wafers with test structures and product chips. High precision DC parametric measurements form a key component to understanding the device level process interactions. One important aspect of DC parametric measurements is the ability to accurately measure currents ranging from pico-amperes for leakage characterization to milli-amperes for transistor IV characterization. Sophisticated test equipment that meets the requirements of high accuracy and high throughput are needed for this purpose. In this paper we present a hybrid tester that addresses these requirements. The novel architecture presented here is scalable and truly parallel. The system is capable of measuring currents from pico-amperes to hundreds of milli-amperes and at the same time provide advanced digital test capabilities.